Browse > Article
http://dx.doi.org/10.14372/IEMEK.2016.11.6.353

Design of Cache Memory System for Next Generation CPU  

Jo, Ok-Rae (GyeongSang National University)
Lee, Jung-Hoon (GyeongSang National University (ERI))
Publication Information
IEMEK Journal of Embedded Systems and Applications / v.11, no.6, 2016 , pp. 353-359 More about this Journal
Abstract
In this paper, we propose a high performance L1 cache structure for the high clock CPU. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to reduce miss ratio, and a way-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is stored into the two-way set associative buffer. For the high performance and fast access time, we propose an one way among two ways set associative buffer is selectively accessed based on the way-select table (WST). According to simulation results, access time can be reduced by about 7% and 40% comparing with a direct cache and Intel i7-6700 with two times more space respectively.
Keywords
High performance CPU; Cache memory; Average memory access time;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 Intel Processor, http://www.intel.com/content/www/us/en/homepage.html
2 Samsung DRAM, http://www.samsung.com/semiconductor/
3 B.S. Jung, J.H. Lee, "Cache memory system for high performance CPU with 4GHz," Journal of the Korea Society of Computer andInformation, Vol. 18, pp. 1-8, 2013 (in Korean).
4 CACTI 4.0, http://www.hpl.hp.com/techreports/2006/HPL-2006-86.pdf
5 C.J. Janraj, T.V. kalyan, T. Warrier, M. Mutya, "Way sharing set associative cache architecture," Proceedings of IEEE International Conference on VLSI Design, pp. 251-256, 2012.
6 D. Rolan, B. Fraguela, R. Doallo, "Adaptive line placement with the set balancing cache," Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 529-540, 2009.
7 C.H. Ting, J.D. Huang, Y.H. Kao, "Cycle-time-aware sequential way-access set-associative cache for low energy consumption," Proceedings of IEEE Asia Pacific Conference on Circuits and Systems, pp. 854-857, 2008.
8 M.R. Guthaus, J.S. Ringenberg, D. Ernst, T.M. Austin, T. Mudge, R.B. Brown, "MiBench: a free, commerically representative embedded benchmark suite," Proceedings of IEEE International Workshop on Workload Characterization, pp. 3-14, 2001.
9 D. Burger, T.M. Austin, "The simplescalar tool set, version 2.0," ACM SIGARCH Computer Architecture News, Vol. 25, pp. 13-25, 1997.