• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.99-100
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• 2009

SGOI 1T-DRAM cells with various Ge mole fractions were fabricated and compared to the SOI 1T-DRAM cell. SGOI 1T-DRAM cells have a higher leakage current than SOI 1T-DRAM cell at subthreshold region. The leakage current due to crystalline defects and interface states at Si/SiGe increased with Ge mole. This phenomenon causes sensing margin and the retention time of SGOI 1T-DRAMs decreased with increase of Ge mole fraction.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.6
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• pp.1175-1177
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• 2011

The SBN thin films were deposited on Pt/Ti/$SiO_2$/Si and p-type Si(100) substrate by rf magnetron sputtering method using $Sr_{0.7}Bi_{2.3}Nb_2O_9$ ceramic target. SBN thin films deposited were annealed at 600~800[$^{\circ}C$] by furnace in oxygen atmosphere during 40min. The polarization characteristics have been investigated to confirm the possibility of the SBN thin films for the application to destructive read out ferroelectric random access memory. The maximum remanent polarization and the coercive voltage are 0.6[${\mu}C/cm^2$], 1.2[V] respectively at annealing temperature of 800[$^{\circ}C$]. The leakage current density was the $2.57{\times}10^{-6}[A/cm^2]$ at an applied voltage of 5[V] at annealing temperature of 650[$^{\circ}C$]. Also, the fatigue characteristics of SBN thin films did not change up to $10^8$ switching cycles.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2000.11a
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• pp.17-20
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• 2000

This study is about a retrograde triple well employed in the Cell tr. of next DRAM and flash memory. triple well structure is formed deep n-well under the light p-well using MeV ion implantation. MeV P implanted deep n-well was observed to show greatly improved characteristics of electrical isolation and soft error. Junction leakage current, however, showed a critical behavior as a function of implantation and annealing conditions. {311} defects were observed to be responsible for the leakage current. {311} defects were generated near the R$\sub$p/ (projected range) region and grown upward to the surface during annealing. This is study on the defect behavior in device region as a function of implantation and annealing conditions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.17-20
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• 2000

This study is about a retrograde triple well employed in the Cell tr. of next DRAM and flash memory. Triple well structure is formed deep n-well under the light p-well using MeV ion implantation. MeV P implanted deep n-well was observed to show greatly improved characteristics of electrical isolation and soft error. Junction leakage current, however, showed a critical behavior as a function of implantation and annealing conditions. {311} defects were observed to be responsible for the leakage current. {311} defects were generated near the R$\_$p/ (Projected range) region and grown upward to the surface during annealing. This is study on the defect behavior in device region as a function of implantation and annealing conditions.

• Journal of the Korean Ceramic Society
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• v.37 no.2
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• pp.168-173
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• 2000

YMnO3 thin films were prepared on Pt/Ti/SiO2/Si substrate by chemical solution deposition method. The films were crystallized by heat-treatment at 85$0^{\circ}C$ for 1 hour. Effects of an annealing atmosphere(O2, Ar, vacuum) on the crystallization behavior and electridcal properties were investigated. YMnO3 thin films annealed under Ar atmosphere showed a superior crystallinity and a very strong c-aix preferred-orientation which was a polar axis. Leakage current density of the films decreased with lowering oxygen partial pressure of the annealing atmosphere. C-V and P-E ferroelectric hysteresis were observed only in the thin film heat-treated under Ar atmosphere.In order to prepare YMnO3 thin films having both low leakage current and ferroelectricity, the annealing atmsphere should be kept under a proper oxygen partial pressure which was about 1 Pa in this work. Leakage current density at 1 volt, dielectric constant($\varepsilon$r), remanent polarization(Pr), and coercive field(Ec) were 1.7$\times$10-8 A/$\textrm{cm}^2$, 25, 1.08$\mu$C/$\textrm{cm}^2$, and 100 kV/cm, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.107-116
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• 1996

Recently, the flash memory has been abstracting great attention in the semiconductor market in the world because of its potential applications as mass storage devices. One of the most significant barriers to the scalling-down of the stacked-gate devices such as EPROM's and flash EEPROM's is the large subthreshold leakage in the unselected cells connected with the bit line of a selected cell in the array during programming. The large subthreshold leakge is majorly due to the capacitive coupling between the floating gates of the unselectd cells and the bit line of selected cell. In this paper, a new programming method to redcue significantly the drain turn-on leakage in the unselected cells during programming has been studied, where a little positive voltage (0.25-0.75V) is applied to the soruce during programming unlike the conventional programming method in which the source is grounded. The resutls of the PISCES simulations and the electrical measurements for the standard EPROM with 0.35.mu.m effective channel length and 1.0.mu.m effective channel width show that the subthreshold leakage in the unselectd cells is significantly large when the source is grounded, whereas it is negligibly small when the source is biased ot a little positive voltage during programming. On the other hadn, the positive bias on the source is found to have little effects on the programming speed of the EPROM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.35-38
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• 2002

In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride， and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.95-96
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• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.8
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• pp.1401-1405
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• 2010

We have successfully demonstrated of metal-insulator-semiconductor (MIS) capacitors with $HfO_2$/p-Si structures. The $HfO_2$ film was grown at $200^{\circ}C$ on H-terminated Si wafer by atomic layer deposition (ALD) system. TEMAHf and $H_2O$ were used as the hafnium and oxygen sources. A cycle of the deposition process consisted of 0.1 s of TEMAHf pulse, 10 s of $N_2$ purge, 0.1 s of $H_2O$ pulse, and 60 s of $N_2$ purge. The 5 nm thick $HfO_2$ layer prepared on Si substrate by ALD exhibited excellent electrical properties, including low leakage currents, no mobile charges, and a good interface with Si.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.51 no.2
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• pp.77-81
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• 2002

In this study, PZT thin films were fabricated using sol-gel processing onto Si/$SiO_2$/Ti/Pt substrates. PZT sol with different Zr/Ti ratio(20/80, 30/70, 40/60, 52/48) were prepared, respectively. The films were fabricated by using the spin-coating method on substrates. The films were heat treated at $450^{\circ}C$, $650^{\circ}C$ by rapid thermal annealing(RTA). The preferred orientation of the PZT thin films were observed by X-ray diffraction(XRD), and Scanning electron microscopy(SEM). All of the resulting PZT thin films were crystallized with perovskite phase. The fine crystallinity of the films were fabricated. Also, we found that the ferroelectric properties from the dielectric constant of the PZT thin films were over 600 degrees, P-E hysteresis constant. And the leakage current densities of films were lower than $10^{-8}A/cm^2$. It is concluded that the PZT thin films by sol-gel process to be convinced of application for ferroelectric memory device.