• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.6
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• pp.445-449
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• 2020

Non-volatile memory is approaching its fundamental limits with the Si₃N₄ storage layer, necessitating the use of alternative materials to achieve a higher programming/erasing speed, larger storage window, and better data retention at lower operating voltage. This limitation has restricted the development of the charge-trap memory, but can be addressed by using high-k dielectrics. The paper reviews the doping of nitrogen, titanium, and yttrium on high-k dielectrics as a storage layer by comparing MONOS devices with different storage layers. The results show that nitrogen doping increases the storage window of the Gd₂O₃ storage layer and improves its charge retention. Titanium doping can increase the charge capture rate of HfO₂ storage layer. Yttrium doping increases the storage window of the BaTiO₃ storage layer and improves its fatigue characteristics. Parameters such as the dielectric constant, leakage current, and speed of the memory device can be controlled by maintaining a suitable amount of external impurities in the device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.7-17
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• 2010

In this paper, an innovative low-power SRAM based on 4-transistor latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. Moreover, the design reduces the leakage current in the memory cells. The proposed SRAM has been demonstrated through 16-kbit test chip fabricated in a 0.18-${\mu}m$ CMOS process. It shows 17.5 ns access at 1.8-V supply while consuming dynamic power of $87.6\;{\mu}W/MHz$ (for read cycle) and $70.2\;{\mu}W/MHz$ (for write cycle). Compared with those of the conventional 6-transistor SRAM, it exhibits the power reduction of 30 % (read) and 42 % (write) respectively. Silicon measurement also confirms that the proposed SRAM achieves nearly 64 % reduction in the total standby power dissipation. This novel SRAM might be effective in realizing low-power embedded memory in future mobile applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.319-322
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• 2003

To match the charge induced by the insulators $CeO_2$ with the remanent polarization of ferro electric SBT thin films, areas of Pt/SBT/Pt (MFM) and those of $Pt/CeO_2/Si$ (MIS) capacitors were ind ependently designed. The area $S_M$ of MIS capacitors to the area $S_F$ of MFM capacitors were varied from 1 to 10, 15, and 20. Top electrode Pt and SBT layers were etched with for various area ratios of $S_M\;/\;S_F$. Bottom electrode Pt and $CeO_2$ layers were respectively deposited by do and rf sputtering in-situ process. SBT thin film were prepared by the metal orgnic decomposition (MOD) technique. $Pt(100nm)/SBT(350nm)/Pt(300nm)/CeO_2(40nm)/p-Si$ (MFMIS) gate structures have been fabricated with the various $S_M\;/\;S_F$ ratios using inductively coupled plasma reactive ion etching (ICP-RIE). The leakage current density of MFMIS gate structures were improved to $6.32{\times}10^{-7}\;A/cm^2$ at the applied gate voltage of 10 V. It is shown that in the memory window increase with the area ratio $S_M\;/\;S_F$ of the MFMIS structures and a larger memory window of 3 V can be obtained for a voltage sweep of ${\pm}9\;V$ for MFMIS structures with an area ratio $S_M\;/\;S_F\;=\;6$ than that of 0.9 V of MFS at the same applied voltage. The maximum memory windows of MFMIS structures were 2.28 V, 3.35 V, and 3.7 V with the are a ratios 1, 2, and 6 at the applied gate voltage of 11 V, respectively. It is concluded that ferroelectric gate capacitors of MFMIS are good candidates for nondestructive readout-nonvolatile memories.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.8 no.3
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• pp.411-418
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• 1998

The thickness dependence of stress electric filed oxide currents has been measured in oxides with thicknesses between 10 nm and 80 nm. The oxide currents were shown to be composed of stress current and transient current. The stress current was composed of stress induced leakage current and dc current. The stress current was caused by trap assisted tunneling through the oxide. The transient current was caused by the tunneling charging and discharging of the trap in the interfaces. The stress current was used to estimate to the limitations on oxide thicknesses. The transient current was used to the data retention in memory devices.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.35-35
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• 2003

Recent progress in the integration of the ferroelectric random access memories (FRAM) has attracted much interest. Strontium bismuth tantalate(SBT) is one of the most attractive materials for use in nonvolatile-memory applications due to low-voltage operations, low leakage current, and its excellent fatigue-free property. High-density FRAMs operated at a low voltage below 1.5V are applicable to mobile devices operated by battery. SBT films thinner than 0.1 #m can be operated at a low voltage, because the coercive voltage (Vc) decreases as the film thickness is reduced. In addition, the thickness of the SBT film will have to be reduced so it can fit between adjacent storage nodes in a pedestal type capacitor in future FRAMs.

• International Journal of Railway
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• v.1 no.1
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• pp.6-11
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• 2008

This paper presents a performance characteristic analysis methodology for a linear induction motor used for a lightweight train. In general, an analytical method cannot provide accurate results in a linear motor because of large airgap, end effect, transverse edge effect, 3-dimensional configurations, large leakage, and so on. Besides, a numerical method requires lots of memory and solving time for transient analysis. However, the suggested methodology which is a kind of hybrid solution with an analytical method and a numerical method is very fast and accurate. Based on the methodology, 3-D FEM analyses for various design schemes of the secondary reaction plate have been done and from the analysis results, the best configuration for an urban railway transit is chosen.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 1999.02a
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• pp.125-128
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• 1999

This paper presents the 2-D analysis of damper transient in superconducting of damper transient in superconducting synchronous generator(SCG) using finite element method. Efficient 2-D analysis model which compensates the leakage flux is proposed for the savign of computation time and memory capacity required in 3-D finite element analysis. The characteristics of damper transient in SCG and the prime role of damper also have been evaluated.

• Journal of the Korean Ceramic Society
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• v.31 no.10
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• pp.1115-1122
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• 1994

ZT/PZT/ZT multi-layered thin films were deposited on silicon substrate by co-sputtering method for FEMFET device application. Effects of Pb/(Zr+Ti) ratio, films thickness, annealing conditions and substrate temperature on the ferroelectric behavior of the multi-layered films were studied. The best memory device characteristics with leakage current of 2$\times$10-8 A/$\textrm{cm}^2$ and breakdown field of about 1 MV/cm could be obtained with ZT(250 $\AA$) / PZT(1000 $\AA$)/ZT(750 $\AA$) multi-layered thin film deposited at 35$0^{\circ}C$ and post-annealed at $700^{\circ}C$ for 120 sec by RTA(Rapid Thermal Annealing).

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.221-224
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• 2000

We have successfully demonstrated metal-ferroel-ectric-insulator-semiconductor (MFIS) devices using Al/LiNbO$_{3}$/SiN/Si structure. The SiN thin films were made into metal -insulator- semiconductor (MIS) devices by thermal evaporation of aluminum source in a dot away on the surface. The interface property of MFIS from 1MHz & quasistatic C-V is good and the memory window width is about 1.5V at 0.2V/s signal voltage sweep rate. The gate leakage current density of MFIS capacitors using a aluminum electrode showed the least value of 1x10$^{-8}$ A/$\textrm{cm}^2$ order at the electric field of 300㎸/cm. And the XRD patterns shows the probability of applications of LN for MFIS devices for FeRAMs on amorphous SiN buffer layer.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2002.05a
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• pp.71-77
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• 2002

The spectrum of impulse response signal which is obtained from an impulse hammer testing is used for frequency response function, nevertheless it has serious faults when the record length for the signal processing is not very long. The faults cannot be avoided with the conventional signal analyzer that is processing all the signals as if they are always periodic. The signals generated by the impact hammer are undoubtedly non-periodic because of the damping, and are acquired for limited recording time due to the memory as well as the computation performance of the signal analyzer. This paper will make clear the relation between the faults and the length of recording time, and propose the way for solving the faults.