• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.55-64
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• 2017

High-capacity, high-definition image applications need to process considerable amounts of data at high speed. Accordingly, users of these applications demand a high-speed parallel execution system. To increase the speed of a parallel execution system, Park (2004) proposed a technique, called MAMS (Multi-Access Memory System), to access data in several execution units without the conflict of parallel processing memories. Since then, many studies on MAMS have been conducted, furthering the technique to MAMS-PP16 and MAMS-PP64, among others. As a memory architecture for parallel processing, MAMS must be constructed in one chip; therefore, a method to achieve the identical functionality as the existing MAMS while minimizing the architecture needs to be studied. This study proposes a method of miniaturizing the MAMS architecture in which the architectures of the ACR (Address Calculation and Routing) circuit and MMS (Memory Module Selection) circuit, which deliver data in memories to parallel execution units (PEs), do not use the MMS circuit, but are constructed as one shift and conditional statements whose number is the same as that of memory modules inside the ACR circuit. To verify the performance of the realized architecture, the study conducted the processing time of the proposed MAMS-PP64 through an image correlation test, the results of which demonstrated that the ratio of the image correlation from the proposed architecture was improved by 1.05 on average.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2395-2403
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• 1998

Memory allocation problem has two independent goals: minimization of number of memories and minimization of number of registers in one memory Our concern is the ordering of the bindings during memory allocation. We formulate and analyze three different memory allocation algorithms b) changing their binding order. It is shown that when we combine these subtasks and solve them simultaneously by heuristic cost function significant savings (up to 20%) can be obtained in the total area of memories.

• Journal of the Korea Society of Computer and Information
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• v.21 no.4
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• pp.1-8
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• 2016

In small embedded systems including IoT devices, memory size is very small and it is important to reduce memory amount for execution of application programs. For multi-threaded applications, stack may consume a large amount of memory because each thread has its own stack of sufficiently large size for worst case. This paper presents an implementation of single stack multi-threading, called SSThread (Single Stack Thread), by sharing a stack for all threads to reduce stack memory size. By using SSThread, multi-threaded applications can be programmed based on normal C language environment and there is no requirement of transporting multi-threading operating systems. It consists of several library functions and various C macro definitions. Even though some functional restrictions in comparison to operating systems supporting complete multi-thread functionalities, it is very useful for small embedded systems with tiny memory size and it is simple to setup programming environment for multi-thread applications.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.10 no.4
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• pp.115-120
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• 2011

Recently flash memory is widely used in various mobile devices as storage medium. Nonvolatile memory can be divided into two categories: NAND- and NOR-type flash memory. NOR flash memory is mainly used to store instruction codes for operation; while NAND for data storage. However, NAND does show more economical benefits, that is, it is approximately 30~40% cheaper than NOR flash. Therefore it can be useful to improve NAND flash performance by replacing NOR flash with NAND flash combining with various buffer systems.

• Journal of the Korea Society of Computer and Information
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• v.22 no.3
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• pp.1-8
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• 2017

In this paper, we propose a new hybrid wear leveling technique for NAND Flash memory, called Time-Aware Wear Leveling (TAWL). Our proposal prolongs the lifetime of NAND Flash memory by using dynamic wear leveling technique which considers the wear level of hot blocks as well as static wear leveling technique which considers the wear level of the whole blocks. TAWL also reduces the overhead of garbage collection by separating hot data and cold data using update frequency rate. We showed that TAWL enhanced the lifetime of NAND flash memory up to 220% compared with previous wear leveling techniques and our technique also reduced the number of copy operations of garbage collections by separating hot and cold data up to 45%.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.122-127
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• 2012

A nano-electro-mechanical (NEM) memory simulator has been developed by using Matlab. The simulator can be used for the prediction of hysterisis curves, applied forces, steady- or transient-state behavior, program/erase energy consumption and potential energy. Predicting NEM memory behavior by simple user interface, the simulator will make the design of NEM memory cells simpler.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.115-122
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• 2004

This paper describe the implementation or the boot loader for the boot system using of memory card. This boot roader consist of the system initialization, CF card checking, CF memory card checking, file system and the program relocator. This boot loader increase the system stability with program consistency checking algorithm in the read phase from the CF memory card. And this system have the compatibility in CF memory card file system, so system manufacturing productivity increase.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.91-94
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• 2008

The designed module save to memory after received Image from CMOS image Sensor(CIS), and set a motion of Encoder module, read from memory per one macroblock each original Image and reference image then supply or save. the time required 470 cycle when processed one macroblock. For designed construct verification, I develop reference Encoder C like JM 9.4 and I proved this module with test vector which achieved from reference encoder C.

• Transactions of the Society of Information Storage Systems
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• v.2 no.4
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• pp.214-218
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• 2006

The focus and tracking servo system has been designed and proposed for the holographic memory of one dimensional spatial light modulator(SLM). The general servo method of conventional ODD system was based and modified for new holographic memory. The pre-grooved disc pattern and special dichroic coating were also included for new design in this research and the final separated optics are expected to be applied to the future general holographic memory as well as the one dimensional SLM holographic memory.

• Journal of the Korea Society of Computer and Information
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• v.23 no.4
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• pp.81-88
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• 2018

In this paper, we present some problems with the Groupware Messenger functionality based on dot net 2.0 and implement a new design structure to solve them. They include memory leakage, slow processing, and client window memory crash. These problems resulted in the inconvenience of using instant messaging and the inefficient handling of office tasks. Therefore, in this paper, instant messaging functionality is implemented according to a new design architecture. The new system upgrades dot net 4.5 for clients and deploys the new features based on MQTT for the messenger server. We verify that the memory leak problem and client window memory crash issues have been eliminated on the system with the new messenger functionality. We measure the amount of time it takes to bind data to a set of messages and evaluate the performance, compared to a given system. Through this comparative evaluation, we can see that the new system is more reliable and performing.