• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.11
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• pp.1041-1049
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• 2012

The transactional memory was proposed to solve the problems of the conventional lock-based synchronization methods in the shared memory multiprocessor system. Various implementation methods for putting the high performance transactional memory to practical use have been continuously studied. However, these studies focus only on the commercialization and performance enhancement of the transactional memory. Besides, there have been few studies to analyze the system overhead of the transactional memory according to the conflict management policy. Thus this paper classifies hardware transactional memory, which is one kind of transactional memories, into four types according to the conflict management policy, and then compares and analyzes their performance and system bus traffic through their modeling and simulation. In addition, the most effective conflict management policy for the hardware transactional memory is presented through these comparison and analysis.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.38-45
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• 2014

This paper proposes a characterization method based on the reference memory to characterize memory compiler quickly and accurately. In order to maintain the accuracy of the memory complier and to minimize characterization time, the proposed method models the trends of the generated memories by selecting the reference memories after analyzing the timing trends of the memory compiler. To validate the proposed method, we characterized the 110nm memory compiler derived from 130nm memroy compiler. The average error rate of the characteristics of the memories generated by the proposed method and SPICE simulation is lower than ${\pm}0.1%$. Furthermore, we designed memory BIST test chips at 110nm and 180nm processes and the results of the function test show that the yield is 98.8% and 98.3%, respectively. Therefore, the proposed method is useful to characterize the memory compiler.

• Sleep Medicine and Psychophysiology
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• v.4 no.1
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• pp.15-28
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• 1997

Longterm memory is encoded in the neuronal connectivities of the brain. The most successful models of human memory in their operations are models of distributed and self-organized associative memory, which are founded in the principle of simulaneous convergence in network formation. Memory is not perceived as the qualities inherent in physical objects or events, but as a set of relations previously established in a neural net by simultaneousy occuring experiences. When it is easy to find correlations with existing neural networks through analysis of network structures, memory is automatically encoded in cerebral cortex. However, in the emergence of informations which are complicated to classify and correlated with existing networks, and conflictual with other networks, those informations are sent to the subcortex including hippocampus. Memory is stored in the form of templates distributed across several different cortical regions. The hippocampus provides detailed maps for the conjoint binding and calling up of widely distributed informations. Knowledge about the distribution of correlated networks can transform the existing networks into new one. Then, hippocampus consolidats new formed network. Amygdala may enable the emotions to influence the information processing and memory as well as providing the visceral informations to them. Cortico-striatal-pallido-thalamo-cortical loop also play an important role in memory function with analysis of language and concept. In case of difficulty in processing in spite of parallel process of informations, frontal lobe organizes theses complicated informations of network analysis through temporal processing. With understanding of brain mechanism of memory and information processing, the brain mechanism of mental phenomena including psychopathology can be better explained in terms of neurobiology and meuropsychology.

• Research in Vestibular Science
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• v.17 no.4
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• pp.134-141
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• 2018

Objectives: We aimed to study the role of vestibular input on spatial memory performance in mice that had undergone bilateral surgical labyrinthectomy, semicircular canal (SCC) occlusion and 4G hypergravity exposure. Methods: Twelve to 16 weeks old ICR mice (n=30) were used for the experiment. The experimental group divided into 3 groups. One group had undergone bilateral chemical labyrinthectomy, and the other group had performed SCC occlusion surgery, and the last group was exposed to 4G hypergravity for 2 weeks. The movement of mice was recorded using camera in Y maze which had 3 radial arms (35 cm long, 7 cm high, 10 cm wide). We counted the number of visiting arms and analyzed the information of arm selection using program we developed before and after procedure. Results: The bilateral labyrinthectomy group which semicircular canal and otolithic function was impaired showed low behavioral performance and spacial memory. The semicircular canal occlusion with $CO_2$ laser group which only semicircular canal function was impaired showed no difference in performance activity and spatial memory. However the hypergravity exposure group in which only otolithic function impaired showed spatial memory function was affected but the behavioral performance was spared. The impairment of spatial memory recovered after a few days after exposure in hypergravity group. Conclusions: This spatial memory function was affected by bilateral vestibular loss. Space-related information processing seems to be determined by otolithic organ information rather than semicircular canals. Due to otolithic function impairment, spatial learning was impaired after exposure to gravity changes in animals and this impaired performance was compensated after normal gravity exposure.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.3
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• pp.837-852
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• 2021

Recurrent neural network (RNN) architectures have been used for language modeling (LM) tasks that require learning long-range word or character sequences. However, the RNN architecture is still suffered from unstable gradients on long-range sequences. To address the issue of long-range sequences, an attention mechanism has been used, showing state-of-the-art (SOTA) performance in all LM tasks. A differentiable neural computer (DNC) is a deep learning architecture using an attention mechanism. The DNC architecture is a neural network augmented with a content-addressable external memory. However, in the write operation, some information unrelated to the input word remains in memory. Moreover, DNCs have been found to perform poorly with low numbers of weight parameters. Therefore, we propose a robust memory deallocation method using a limited retention vector. The limited retention vector determines whether the network increases or decreases its usage of information in external memory according to a threshold. We experimentally evaluate the robustness of a DNC implementing the proposed approach according to the size of the controller and external memory on the enwik8 LM task. When we decreased the number of weight parameters by 32.47%, the proposed DNC showed a low bits-per-character (BPC) degradation of 4.30%, demonstrating the effectiveness of our approach in language modeling tasks.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.66-73
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• 2015

IFFT is one of the key components in OFDM-based communication systems. In this paper, we propose a new memory efficient IFFT design method for OFDM-based communication systems, based on a mapping of three IFFT input signals which consist of modulated data, pilot and null signals. The proposed method focuses on reducing the memory size in the bit-reversal block which requires the largest number of memory cells in IFFT architectures. To reduce the memory size, we propose a selection mapping method based on decimation-in-time (DIT) algorithm. It is shown that the proposed method achieves a memory reduction of about 50% compared to conventional methods.

• Journal of the Korean Society for information Management
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• v.20 no.4 s.50
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• pp.91-111
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• 2003

This paper shows that digital libraries can be understood through STIN models which emphasize interactions among components in networks. The enrollment strategies in the American Memory make human and non-human factors interact. Specifically, this paper articulates that the relationships between users and collections, between users and staff, and between users and users are closely linked through the strategies . Observing the linkages among these components ,this paper found that the enrollment processes not only draw users to the American Memory, but also alter roles of components and creates new roles and players for them. The alterations of roles and the resulting changes of relationships among components mean that digital libraries lead to transform the grounding of knowledge works in a society.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10B
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• pp.1648-1664
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• 2000

This paper proposes a real-time dynamic storage allocation algorithm QSHF(quick-segregated-half-fit) that provides various memory allocation policies. that manages a free block list per each word size for memory requests of small size good(segregated)-fit policy that manages a free list per proper range size for medium size requests and half-fit policy that manages a free list per proper range size for medium size requests and half-fit policy that manages a free list per each power of 2 size for large size requests. The proposed algorithm has the time complexit O(1) and makes us able to easily estimate the worst case execution time(WCET). This paper also suggests two algorithm that finds the proper free list for the requested memory size in predictable time and if the found list is empty then finds next available non-empty free list in fixed time. In order to confirm efficiency of the proposed algorithm we simulated the memory utilization of each memory allocation policy. The simulation result showed that each policy guarantees the constant WCET regardless of memory size but they have trade-off between memory utilization and list management overhead.

• Journal of Information Processing Systems
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• v.16 no.3
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• pp.588-598
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• 2020

An alternative state estimation filtering algorithm is designed for continuous time systems with noises as well as control input. Two kinds of estimation filters, which have different measurement memory structures, are operated selectively in order to use both filters effectively as needed. Firstly, the estimation filter with infinite memory structure is operated for a certain continuous time system. Secondly, the estimation filter with finite memory structure is operated for temporarily uncertain continuous time system. That is, depending on the presence of uncertainty, one of infinite memory structure and finite memory structure filtered estimates is operated selectively to obtain the valid estimate. A couple of test variables and declaration rule are developed to detect uncertainty presence or uncertainty absence, to operate the suitable one from two kinds of filtered estimates, and to obtain ultimately the valid filtered estimate. Through computer simulations for a continuous time aircraft engine system with different measurement memory lengths and temporary model uncertainties, the proposed state estimation filtering algorithm can work well in temporarily uncertain as well as certain continuous time systems. Moreover, the proposed state estimation filtering algorithm shows remarkable superiority to the infinite memory structure filtering when temporary uncertainties occur in succession.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.4
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• pp.1922-1940
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• 2019

IP address lookup is a function to determine nexthop for a given destination IP address. It takes an important role in modern routers because of its computation time and increasing Internet traffic. TCAM-based IP lookup approaches can exploit the capability of parallel searching but have a limitation of its size due to latency, power consumption, updatability, and cost. On the other hand, multibit trie-based approaches use SRAM which has relatively low power consumption and cost. They reduce the number of memory accesses required for each lookup, but it still needs several accesses. Moreover, the memory efficiency and updatability are proportional to the number of memory accesses. In this paper, we propose a novel architecture using an Indexed Multibit Trie (IMT) which is based on combined TCAM and SRAM. In the proposed architecture, each lookup takes at most two memory accesses. We present how the IMT is constructed so as to be memory-efficient and fast updatable. Experiment results with real-world forwarding tables show that our scheme achieves good memory efficiency as well as fast updatability.