• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.567-570
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• 2001

In this paper, we proposed flash memory design method for image and voice recoder based on the standard imageㆍvoice codec algorithm. For implementation of this method we designed image voice browser which is application system of flash memory and card using GDS30C6001 USB controller. To process image and voice data we designed root directory of image and voice files repectively. To extend application of image and voice data we added various information to the system.

• Journal of Internet of Things and Convergence
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• v.9 no.3
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• pp.81-86
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• 2023

SSD (solid state disk), which is flash memory-based storage device, has the advantages of high density and fast data processing. Therefore, it is being utilized as a storage device for high-capacity data storage systems that manage rapidly increasing big data. However, flash memory, a storage media, has a physical limitation that when the write/erase operation is repeated more than a certain number of times, the cells are worn out and can no longer be used. In this paper, we propose a method for converting defective multi-bit cells into single-bit cells to reduce the defect rate of flash memory and extend its lifetime. The proposed idea distinguishes the defects and treatment methods of multi-bit cells and single-bit cells, which have different physical characteristics but are treated as the same defect, and converts the expected defective multi-bit cells into single-bit cells to improve the defect rate and extend the overall lifetime. Finally, we demonstrate the effectiveness of our proposed idea by measuring the increased lifetime of SSD through simulations.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.78-83
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• 2023

This paper proposes a lightweight trace-driven Processing-In-Memory (PIM) simulator, TP-Sim. TP-Sim is a General Purpose PIM (GP-PIM) simulator that evaluates various PIM system performance-related metrics. Based on instruction and memory traces extracted from the Intel Pin tool, TP-Sim can replay trace files for multiple models of PIM architectures to compare its performance. To verify the availability of TP-Sim, we estimated three different system configurations on the STREAM benchmark. Compared to the traditional Host CPU-only systems with conventional memory hierarchy, simple GP-PIM architecture achieved better performance; even the Host CPU has the same number of in-order cores. For further study, we also extend TP-Sim as a part of a heterogeneous system simulator that contains CPU, GPGPU, and PIM as its primary and co-processors.

• Proceedings of the Korean Society of Computer Information Conference
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• 2017.07a
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• pp.275-278
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• 2017

기존의 임베디드 기기의 하드웨어는 리눅스의 장점에도 불구하고 임베디드 기기들의 프로세서나 메모리 등의 하드웨어 자원이 Built-in 형태로 제공되어 시스템 운용 환경 변화에 맞춘 대응이 어렵다. 이러한 문제를 해결하기 위해 본 논문에서는 i.MX6Q SABRE Board for Smart Devices를 참조하여 메모리를 교체할 수 있도록 SO-DIMM을 장착하고 PCIe 이더넷을 추가한 개발보드를 만들었다. 그리고 개발보드에 추가 및 변경 된 하드웨어 디바이스를 활성화한 새로운 임베디드 시스템을 이식하는 방법을 제시한다. 구현 및 성능 분석 결과 새로운 임베디드 시스템에서 운용자는 시스템 운용 시 환경 변화에 대응하여 메모리를 바꾸어 장착할 수 있게 되었고 이로 인해 시스템의 요구사항에 따라 자원의 확정성 및 유연성이 높아짐을 확인하였다.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.959-961
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• 2003

In this paper, we describe implemented DMAC (Direct Memory Access Controller) architecture on Altera's $Excalibur^{TM}$ that includes industry-standard $ARM922T^{TM}$ 32-bit RISC processor core operating at 200 MHz. We implemented DMAC based on AMBA (Advanced Micro-controller Bus Architecture) AHB (Advanced Micro-performance Bus) interface. Implemented DMAC has 8-channel and can extend supportable channel count according to user application. We used round-robin method for priority selection. Implemented DMAC supports data transfer between Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory. The max transfer count is 1024 per a time and it can support byte, half-word and word transfer according to AHB protocol (HSIZE signals). We implemented with VHDL and functional verification using $ModelSim^{TM}$. Then, we synthesized using $LeonardoSpectrum^{TM}$ with Altera $Excalibur^{TM}$ library. We did FPGA P&R and targeting using $Quartus^{TM}$. We can use implemented DMAC module at any system that needs high speed and broad bandwidth data transfers.

• Journal of KIISE:Software and Applications
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• v.37 no.10
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• pp.760-767
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• 2010

There are many memory leak detection tools. However, programmers, who develop very large programs, tend to avoid testing their programs with memory leak detection tools since these tools require runtime and space overheads. Thus, we present a memory leak detection technique which enables programmers to test their modules in their unit test phase with low overheads. To achieve this goal, we extend the existing cyclic memory allocation technique and evaluate our memory leak detection technique on a tiny DBMS. In our experiments, we find our tool has reasonably low runtime and space overheads and it reports only a small number of false positives.

• Journal of the Semiconductor & Display Technology
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• v.21 no.3
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• pp.1-6
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• 2022

Modern computer systems usually have special hardware for operations used in deep learning workload even edge computing environment. Non-volatile memories (NVMs) have been considered for alternative memory storage because they consume little static energy and occupy small area. However, there is a problem for NVMs to be directly adopted. An NVM cell has limited write endurance, so that the lifetime of NVM-based memory system is much shorter than that of conventional memory system. To overcome this problem for the deep learning system, this paper proposes a novel method to extend the lifetime based on the analysis of the deep learning workloads. If an incoming block has more than a predefined number of frequently used values, the cacheline is defined as write friendly block. During the victim selection, the cacheline has lower possibility to be chosen as victim. The experimental results show that the lifetime is increased by about 50% and energy consumption is decreased by 3% with a little performance hurt.

• Journal of Korea Multimedia Society
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• v.12 no.2
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• pp.165-177
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• 2009

Embedded database systems (EDBMS) based on NAND flash memories are widely adopted for logging data on sensor nodes. Since write and erase operations of a flash memory are time consuming compared to read operations and wear memory cells, it is important to reduce these operations to enhance the EDBMS performance and to extend the memory life. In this paper, we propose a delayed write scheme to archive this goal. Proposed scheme stores updated parts of database pages into delayed write records to reduce the database page writes. By doing that, it decreases write and erase operations on a flash memory. Therefore, the proposed scheme enhances the logging performance of a write-intensive EDBMS on a sensor node and extends the flash memory life.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.201-208
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• 2016

Non-volatile counter is a counter that maintains the value without external power supply. It has been used for the applications related to warranty issues to count and record certain events such as power cycles, operating time, hard resets, and timeouts. It has been conventionally implemented with volatile memory-based counter and battery backup or non-volatile memory such as EEPROM. Both of them have a lifetime issue due to the limited lifetime of the battery and the endurance of the non-volatile memory cells, which incurs significant redundancy in design. In this paper, we introduce a hybrid architecture of volatile (SRAM) and non-volatile memory (EEPROM) cells to achieve required lifetime of the non-volatile counter with smaller cost. We conduct a design space exploration of the proposed hybrid architecture with the parameters of various kinds of non-volatile memories. The analysis result shows that the proposed hybrid non-volatile counter can extend the lifetime up to 6 times compared to the battery-backup volatile memory-based implementation.

• Transactions on Electrical and Electronic Materials
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• v.11 no.6
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• pp.243-248
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• 2010

The emergence of different and disparate materials together with the convergence of both the 'old' and 'emerging' technologies is paving the way for integration of heterogeneous technologies that are likely to extend the limitations of silicon technology beyond the roadmap envisaged for complementary metal-oxide semiconductor. Formulation of new information processing concepts based on novel aspects of nano-scale based materials is the catalyst for new nanoarchitectures driven by a different perspective in realization of novel logic devices. The memory technology has been the pace setter for silicon scaling and thus far has pave the way for new architectures. This paper provides an overview of the inevitability of heterogeneous integration of technologies that are in their infancy through initiatives of material physicists, computational chemists, and bioengineers and explores the options in the spectrum of novel non-volatile memory technologies considered as forerunner of new logic devices.