• Journal of Korea Multimedia Society
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• v.3 no.4
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• pp.407-415
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• 2000

The ultimate goal of flow control in the semiconductor fabrication process, one of the most equipment-intensive and complex manufacturing process, is to reduce lead time and work in process. In this paper, we propose stand alone layout in the form of job shop using group technology to improve the Productivity and eliminate the inefficiency in FMS (flexible manufacture system). The performance of stand alone layout and in-line layout are analyzed and compared while varying number of device variable chanties. The analysis of in-line layout is obtained by examining its adoption in the memory products of semiconductor factory. The comparison is performed through simulation using ProSys; a window 95 based discrete system simulation software, as a tool for comparing performance of two proposed layouts. The comparison demonstrates that when the number of device variable change is small, in-line layout is more efficient in terms of production Quantity. However, as the number of device variable change is more than 14 times, stand alone layout prevails over in-line layout.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.108-109
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• 2012

This talk will begin with the demonstration of facile synthesis of silicon nanostructures using the magnesiothermic reduction on silica nanostructures prepared via self-assembly, which will be followed by the characterization results of their performance for energy storage. This talk will also report the fabrication and characterization of highly porous, stretchable, and conductive polymer nanocomposites embedded with carbon nanotubes (CNTs) for application in flexible lithium-ion batteries. It will be presented that the porous CNT-embedded PDMS nanocomposites are capable of good electrochemical performance with mechanical flexibility, suggesting these nanocomposites could be outstanding anode candidates for use in flexible lithium-ion batteries. Directed self-assembly (DSA) of block copolymers (BCPs) can generate uniform and periodic patterns within guiding templates, and has been one of the promising nanofabrication methodologies for resolving the resolution limit of optical lithography. BCP self-assembly processing is scalable and of low cost, and is well-suited for integration with existing semiconductor manufacturing techniques. This talk will introduce recent research results (of my research group) on the self-assembly of Si-containing block copolymers for the achievement of sub-10 nm resolution, fast pattern generation, transfer-printing capability onto nonplanar substrates, and device applications for nonvolatile memories. An extraordinarily facile nanofabrication approach that enables sub-10 nm resolutions through the synergic combination of nanotransfer printing (nTP) and DSA of block copolymers is also introduced. This simple printing method can be applied on oxides, metals, polymers, and non-planar substrates without pretreatments. This talk will also report the direct formation of ordered memristor nanostructures on metal and graphene electrodes by the self-assembly of Si-containing BCPs. This approach offers a practical pathway to fabricate high-density resistive memory devices without using high-cost lithography and pattern-transfer processes. Finally, this talk will present a novel approach that can relieve the power consumption issue of phase-change memories by incorporating a thin $SiO_x$ layer formed by BCP self-assembly, which locally blocks the contact between a heater electrode and a phase-change material and reduces the phase-change volume. The writing current decreases by 5 times (corresponding to a power reduction of 1/20) as the occupying area fraction of $SiO_x$ nanostructures varies.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.88-93
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• 2023

As the demand for High Bandwidth Memory (HBM) increases and the handling capability of larger wafers expands, ensuring reliable Total Thickness Variation (TTV) measurement for stacked wafers becomes essential. This study presents the design of a measurement module capable of measuring TTV across the entire area of a 300mm wafer, along with estimating potential mechanical measurement errors. The module enables full-area measurement by utilizing a center chuck and lift pin for wafer support. Modal analysis verifies the structural stability of the module, confirming that both the driving and measuring parts were designed with stiffness exceeding 100 Hz. The mechanical measurement error of the designed module was estimated, resulting in a predicted measurement error of 1.34 nm when measuring the thickness of a bonding wafer with a thickness of 1,500 ㎛.

• Journal of the Korea Safety Management & Science
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• v.6 no.4
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• pp.155-170
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• 2004

Among the semiconductor If-chips, unlike memory chips, a majority of Application Specific IC(ASIC) products are produced by customer orders, and meeting the customer specified due date is a critical issue for the case. However, to the one who understands the nature of semiconductor manufacturing, it does not take much effort to realize the difficulty of meeting the given specific production due dates. Due to its multi-layered feature of products, to be completed, a semiconductor product(called device) enters into the fabrication manufacturing process(FAB) repeatedly as many times as the number of the product specified layers, and fabrication processes of individual layers are composed with similar but not identical unit processes. The unit process called photo-lithography is the only process where every layer must pass through. This re-entrant feature of FAB makes predicting and planning of due date of an ordered batch of devices difficult. Parallel machines problem in the photo process, which is bottleneck process, is solved with restricted roll out algorithm. Roll out algorithm is a method of solving the problem by embedding it within a dynamic programming framework. Restricted roll out algorithm Is roll out algorithm that restricted alternative states to decrease the solving time and improve the result. Results of simulation test in condition as same as real FAB facilities show the effectiveness of the developed algorithm.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.10 no.4
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• pp.97-103
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• 2001

The study on the high-speed machine tool is very important for the improvement of productivity since it can shortens cutting and non-cutting time. Especially, high speed of feed drive system is the major research field. In the industries of the advanced countries, the feed drive systems at the speed of 60 m/min have been already developed based on the high lead ball screws. In this study, a high speed feed drive system at the speed of 60 m/ min has been developed, and its movements characteris-tics are investigated. As the movement characteristics, positioning accuracy, angular accuracy, straightness and micro step-response are measured. Thermal characteristics of the system is also discussed. For measuring the movement characteris-tics, a laser interferometer, a memory-based Hi-coder and a cooling device are used. The experimental results confirm that the movement characteristics and the thermal behavior of the system are satisfactory in the aspect of accuracy and stability.

• Electrical & Electronic Materials
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• v.11 no.11
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• pp.46-52
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• 1998

Barium titanate owes its great importance to the fact that its dielectric constant is about 100 times higher than that of conventional dielectric materials provided its compositional and structural purity is extremely high. The value of crystalline BaTiO3 bodies as used, for instance, in computer elements, magnetic amplifiers, memory device, ets., depend on boththe compositional and the structural purity of the BaTiO3 crystals. This purity will, in turn, depend on the purity of the raw materials used in manufacturing the BaTiO3 compound and on the particularmethods of manufacture which determine the size, homogeneity, and the structural purity of the crystals. This paper reviews the important theoretical considerations, processing techniques and applications related to sol-gel derived thin films.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.1-7
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• 2023

Recently, in the semiconductor industry, memory device market is focusing on producing ultra-thin wafers for high integration. In the wafer manufacturing process, wafers after backgrinding and CMP process must be picked up as individual dies and subjected to be peeled off from the dicing tape. However, ultra-thin dies are vulnerable to the possibility of breakage and failure in their thickness and size. This research studies the mechanism of peeling a die with a high-aspect ratio using a thermopneumatic method instead of a die ejector with physical pins. Setting compressed air and the temperature as main factors, we determine the success of the digester using thermopneumatic system and analyze the good die to find the possibility of making mass-production equipment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.38-49
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• 2006

In this paper, a novel concept based on embedded processor and reconfigurable logic is proposed for efficient manufacturing test and design verification. Unlike traditional gap between design verification and manufacturing test, proposed concept is to combine both design verification and manufacturing test. The semiconductor chip which is using the proposed concept is named "SwToC" and SwToC stands for System with Test On a Chip. SwToC has two main features. First, it has functional verification function on a chip and this function could be made by using embedded processor, reconfigurable logic and memory. Second, it has internal ATE on a chip and this feature also could be made by the same architecture. To evaluate the proposed SwToC, we have implemented SwToC using commercial FPGA device with embedded processor. Experimental results showed that the proposed chip is possible for real application and could have faster verification time than traditional simulation method. Moreover, test could be done using low cost ATE.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.689-695
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• 2002

Film compositions are needed in semiconductor manufacturing for such diverse application as production tool qualifications and process development. Surface and interface information is generally provided with Auger electron spectroscopy(AES). In this paper, WSix films were analyzed for structural, electrical, and compositional properties of tungsten silicide thin films produced by low pressure chemical vapor deposition as a function of temperature, DCS post flow, shower head life time, and the silicon to tungsten ratios have been investigated. We find that Si/W composition ratio is increased in the surface and interface of WSix thin films by the DCS post flow process and increasing deposition temperature, respectively. The results obtained in this study are also applicable to process control of WSix deposition for memory device fabrication.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 1998.04b
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• pp.6-6
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• 1998

In 1957, the first magnetic disk drive compatible with a movable head was introduced as an external file memory device for computer system. Since then, magnetic disks have been improved by increasing the recording density, which has brought about the development of a high performance thin film magnetic head. The thin film magnetic head has a magnetic circuit on a ceramic substrate using IC technology. The physical property of the substrate material is very important because it influences the tribology of head/disk interface and also manufacturing process of the head. $Al_{2}O_{3}$-TiC ceramics, so called ALTIC, is known to be one of the best substrate materials which satisfies this property requirement. Even though the head is not in direct contact with the disk, frequent instantaneous contacts are unavoidable due to its high rotating speed and the close gap between them. This may cause damage in the magnetic recording media and, thus, it is very important that the magnetic head has a good wear resistance. $Al_{2}O_{3}$-TiC ceramics has an excellent tribological property in head/disk interface. Manufacturing process of thin film head is similar to that of IC, which requires extremely smooth and flat surface of the substrate. The substrate must be readily sliced into the heads without chipping. $Al_{2}O_{3}$-TiC ceramics has excellent machineability and mechanical properties. $Al_{2}O_{3}$-TiC ceramics was first developed at Nippon Tungsten Co. as cutting tool materials in 1968, which was further developed to be used as the substrate materials for thin film head in collaboration with Sumitomo Special Metals Co., Ltd. in 1981. Today, we supply more than 60% of the substrates for thin film head market in the world. In this paper, we would like to present the sintering process of $Al_{2}O_{3}$-TiC ceramics and its property in detail.