• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.6
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• pp.391-397
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• 2015

Nonvolatile memories in memory hierarchy have been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU. In this paper, we study the use of a new type of nonvolatile memories - the Phase Change Memory (PCM) with a DRAM buffer system as the main memory. Our design reduced the total energy of a DRAM main memory of the same capacity by 80%. These results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.3
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• pp.184-193
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• 2007

Flash memory adoption in the mobile devices is increasing or vanous multimedia services such as audio, videos, and games. Although the traditional research issues such as out-place update, garbage collection, and wear-leveling are important, the performance, memory usage, and fast mount issues of flash memory file system are becoming much more important than ever because flash memory capacity is rapidly increasing. In this paper, we address the problems of the existing log-based flash memory file systems analytically and propose an efficient log-based file system, which produces higher performance, less memory usage and mount time than the existing log-based file systems. Our ideas are applied to a well-known log-based flash memory file system (YAFFS2) and the performance tests are conducted by comparing our prototype with YAFFS2. The experimental results show that our prototype achieves higher performance, less system memory usage, and faster mounting than YAFFS2, which is better than JFFS2.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.5 no.1
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• pp.60-69
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• 1980

The computerized analysis of complicated circuits requires large memory capacity and considerable length of time. In order to enhance the efficiency of memory capacity and the executing time, Sparse Matrix is applied to the solution of simultaneous equations required for the analysis of amplification circuit. The optimization Subroutine, FMFP is utilized for the decision of optimum element parameters of an equalizer amplifier.

• Proceedings of the KSR Conference
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• 2010.06a
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• pp.1068-1074
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• 2010

In high speed railway, event recorder is essential system for analyzing the cause of train accident. It stores train operation sent by train control system in safe memory unit. Crash protected memory, the safe memory unit for event recorder, keeps the stored contents from severe environment. For crash protected memory, we have designed the architecture of concrete enclosure and controller board. Proposed system provides large volume of memory capacity and fault tolerance architecture. For checking the characteristics of proposed crash protected memory specification, the simulation is executed. Simulation results shows the designed crash protected memory meets all requirements.

• International Journal of Internet, Broadcasting and Communication
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• v.14 no.1
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• pp.188-193
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• 2022

The energy efficiency of memory systems is an important task in designing future computer systems as memory capacity continues to increase to accommodate the growing big data. In this article, we present an energy-efficient last-level cache management policy for future mobile systems. The proposed policy makes use of low-power PCM (phase-change memory) as the main memory medium, and reduces the amount of data written to PCM, thereby saving memory energy consumptions. To do so, the policy keeps track of the modified cache lines within each cache block, and replaces the last-level cache block that incurs the smallest PCM writing upon cache replacement requests. Also, the policy considers the access bit of cache blocks along with the cache line modifications in order not to degrade the cache hit ratio. Simulation experiments using SPEC benchmarks show that the proposed policy reduces the power consumption of PCM memory by 22.7% on average without degrading performances.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.79-89
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• 2014

It has been an increase in consumers who want a high-capacity and fast speed by the newly diffused mobile device(Smart phones, Ultra books, Tablet PC). As a result, the demand for Flash Memory is constantly increasing. Flash Memory is separated by a NAND-type and NOR-type. NAND-type Flash Memory speed is slow, but price is cheaper than the NOR-type Flash Memory. For this reason, NAND-type Flash Memory is widely used in the mobile market. So Fault Detection is very important for Flash Memory Test. In this paper, Proposed PMBIST for Pattern Test of NAND-type Flash Memory improved Fault detection.

• Korean Journal of Biological Psychiatry
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• v.11 no.2
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• pp.155-164
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• 2004

Objective:The present study examined the association between basic neurocognitive functions and emotional recognition in chronic schizophrenia. Furthermore, to Investigate cognitive variable related to emotion recognition in Schizophrenia. Methods:Forty eight patients from the Yongin Psychiatric Rehabilitation Center were evaluated for neurocognitive function, and Emotional Recognition Test which has four subscales finding emotional clue, discriminating emotions, understanding emotional context and emotional capacity. Measures of neurocognitive functioning were selected based on hypothesized relationships to perception of emotion. These measures included:1) Letter Number Sequencing Test, a measure of working memory;2) Word Fluency and Block Design, a measure of executive function;3) Hopkins Verbal Learning Test-Korean version, a measure of verbal memory;4) Digit Span, a measure of immediate memory;5) Span of Apprehension Task, a measure of early visual processing, visual scanning;6) Continuous Performance Test, a measure of sustained attention functioning. Correlation analyses between specific neurocognitive measures and emotional recognition test were made. To examine the degree to which neurocognitive performance predicting emotional recognition, hierarchical regression analyses were also made. Results:Working memory, and verbal memory were closely related with emotional discrimination. Working memory, Span of Apprehension and Digit Span were closely related with contextual recognition. Among cognitive measures, Span of Apprehension, Working memory, Digit Span were most important variables in predicting emotional capacity. Conclusion:These results are relevant considering that emotional information processing depends, in part, on the abilities to scan the context and to use immediate working memory. These results indicated that mul- tifaceted cognitive training program added with Emotional Recognition Task(Cognitive Behavioral Rehabilitation Therapy added with Emotional Management Program) are promising.

• Journal of Korea Multimedia Society
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• v.19 no.7
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• pp.1179-1187
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• 2016

Through the rapid development of latest hardware technology, high performance as well as miniaturized size is the essentials of embedded system to meet various requirements from the society. It raises possibilities of genuine realization of IoT environment whose size and battery must be considered. However, the limitation of battery persistency and capacity restricts the long battery life time for guaranteeing real-time system. To maximize battery life time, low power technology which lowers the power consumption should be highly required. Previous researches mostly highlighted improving one single type of memory to increase ones efficiency. In this paper, reversely, considering multiple memories to optimize whole memory system is the following step for the efficient low power embedded system. Regarding to that fact, this paper suggests the study of volatile memory, whose capacity is relatively smaller but much low-powered, and non-volatile memory, which do not consume any standby power to keep data, to maximize the efficiency of the system. By executing function in specific memories, non-volatile and volatile memory, the quantitative analysis of power consumption is progressed. In spite of the opportunity cost of all of theses extra works to locate function in volatile memory, higher efficiencies of both power and energy are clearly identified compared to operating single non-volatile memory.

• Journal of Oriental Neuropsychiatry
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• v.10 no.1
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• pp.1-15
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• 1999

The effects of Sahyangsohapwon on the enhancement of learning and memory of AD model rats were studied with Morris water maze and radial arm maze. Sample group was electrolytically lesioned on nbM, and then daily treated with the medicine for two months. Control group with nbM lesion, and sham group with the sham operation were treated the vehicle for same duration. The following results were observed. In the learning trials of Morris water maze, all three groups were improved in learning capacity as trials were repeated, but the sham group showed more prominent improvement in learning compared with the control group(p<0.01). 2. In memory retention test of Morris water maze, the sham group marked more significant improvement statistically in memory retention compared with the control group(p<0.05). 3. In the learning of radial arm maze, the sham group shows better learning capacity significantly compared with the control group(p<0.05). With the experimental results above, Sahyangsohapwon can be supposed to have the improving effects on the learning and memory of AD rats induced by electronical injury of nbM.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.9
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• pp.3396-3411
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• 2015

Sensors used in Wireless Sensor Networks (WSN) have mostly limited capacity which affects the performance of their applications. One of the data-gathering methods is to use mobile sinks to visit these sensors so that they can save their limited battery energies from forwarding data packages to static sinks. The main disadvantage of employing mobile sinks is the delay of data collection due to relative low speed of mobile sinks. Since sensors have very limited memory capacities, whenever a mobile sink is too late to visit a sensor, that sensor's memory would be full, which is called a 'memory overflow', and thus, needs to be purged, which causes loss of collected data. In this work, a method is proposed to generate mobile sink tours, such that the number of overflows and the amount of lost data are minimized. Moreover, the proposed method does not need either the sensor locations or sensor memory status in advance. Hence, the overhead stemmed from the information exchange of these requirements are avoided. The proposed method is compared with a previously published heuristic. The simulation experiment results show the success of the proposed method over the rival heuristic with respect to the considered metrics under various parameters.