• 아태비즈니스연구
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• 제13권2호
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• pp.23-37
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• 2022

Purpose - The purpose of this paper is to analyze the dynamic factors of the daily FX implied volatility based on the fractional integration methods focusing on long memory feature and structural changes. Design/methodology/approach - This paper uses the daily FX implied volatility data of the EUR-USD and the JPY-USD exchange rates. For the fractional integration analysis, this paper first applies the basic ARFIMA-FIGARCH model and the Local Whittle method to explore the long memory feature in the implied volatility series. Then, this paper employs the Adaptive-ARFIMA-Adaptive-FIGARCH model with a flexible Fourier form to allow for the structural changes with the long memory feature in the implied volatility series. Findings - This paper finds statistical evidence of the long memory feature in the first two moments of the implied volatility series. And, this paper shows that the structural changes appear to be an important factor and that neglecting the structural changes may lead to an upward bias in the long memory feature of the implied volatility series. Research implications or Originality - The implied volatility has widely been believed to be the market's best forecast regarding the future volatility in FX markets, and modeling the evolution of the implied volatility is quite important as it has clear implications for the behavior of the exchange rates in FX markets. The Adaptive-ARFIMA-Adaptive-FIGARCH model could be an excellent description for the FX implied volatility series

• 제어로봇시스템학회논문지
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• 제13권6호
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• pp.519-524
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• 2007

The OBC(on-board computer) of a satellite which plays a role of the controller for the satellite should be equipped with preventive measures against transient errors caused by SEU(single event upset). Since memory devices are pretty much susceptible to these transient errors, it is essential to protect memory devices against SFU. A common method exploits an error detection and correction code and additional memory devices, combined with periodic memory scrubbing. This paper proposes an effective memory scrubbing scheme for the OBC of STSAT-2. The memory system of the OBC is briefly mentioned and the reliability of the information stored in the memory system is analyzed. The result of the reliability analysis shows that there exist optimal scrubbing periods achieving the maximum reliability for allowed overall scrubbing overhead and they are dependent on the significance of the information stored. These optimal scrubbing periods from a reliability point of view are derived analytically.

• 동의신경정신과학회지
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• 제28권4호
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• pp.359-371
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• 2017

Objectives: The objective of this study was to review the effect of oral administration of herbal medicines on the improvement of memory in Alzheimer's disease animal model reported in Korean domestic journals. Methods: The Korean databases (Koreantk, KISS) were searched with memory as a popular search term. During the searches, only animal study reports were reviewed. Data of animal models, intervention, observation methods of measuring indicators were extracted from the databases. Results: Typically, 36 articles were reviewed. Twenty-two studies used scopolamine to induce Alzheimer's disease, 24 studies used complex herbal medicines, and 12 studies used simple herbal medicines. Polygalae Radix and Acori Rhizoma were the most frequently used herbal medicines to improve memory in Alzheimer model. To evaluate the effect of herbal medicines, 36 studies used macroscopy, 16 studies used molecular biological analysis, 21 studies used biochemical analysis, 15 studies used histological analysis, and 11 studies used hematological analysis. Each study showed significant improvement with respect to memory indicators. Conclusions: Overall, the results suggest that treatment employing herbal medicines is an effective option to treat memory impairment in Alzheimer's disease.

• International journal of advanced smart convergence
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• 제6권1호
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• pp.39-43
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• 2017

As the industry grows, the amount of data grows exponentially, and data analysis using these serves as a predictable solution. As data size increases and processing speed increases, it has begun to be applied to new fields by combining artificial intelligence technology as well as simple big data analysis. In this paper, we propose a method to quickly apply a machine learning based algorithm through efficient resource allocation. The proposed algorithm allocates memory for each attribute. Learning Distinct of Attribute and allocating the right memory. In order to compare the performance of the proposed algorithm, we compared it with the existing K-means algorithm. As a result of measuring the execution time, the speed was improved.

• ETRI Journal
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• 제32권4호
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• pp.642-644
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• 2010

With the rapid increase occurring in both the capacity and density of memory products, test and repair issues have become highly challenging. Memory repair is an effective and essential methodology for improving memory yield. An SoC utilizes built-in redundancy analysis (BIRA) with built-in self-test for improving memory yield and reliability. This letter proposes a new heuristic algorithm and new hardware architecture for the BIRA scheme. Experimental results indicate that the proposed algorithm shows near-optimal repair efficiency in combination with low area and time overheads.

• 한국어학
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• 제79권
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• pp.91-116
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• 2018

This paper aims at proposing issues of breath and memory in speech based on the quantitative analysis of breath groups and pause units in Korean. As a human being, we have two kinds of limitations on continuing speech; breath and memory. The prosodic structure and temporal structure of spontaneous speech data from six speakers were closely examined. One of the main findings of the present study is that the prosodic structure and temporal structure of Korean appears to reflect the breath and memory problems in speech.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.142-148
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• 2023

In this paper, we identify performance issues in executing compute kernels from PolyBench, which includes compute kernels that are the core computational units of various data-intensive workloads, such as deep learning and data-intensive applications, on Processing-in-Memory (PIM) devices. Therefore, using our in-house simulator, we measured and compared the various performance metrics of workloads based on traditional out-of-order and in-order processors with Processing-in-Memory-based systems. As a result, the PIM-based system improves performance compared to other computing models due to the short-term data reuse characteristic of computational kernels from PolyBench. However, some kernels perform poorly in PIM-based systems without a multi-layer cache hierarchy due to some kernel's long-term data reuse characteristics. Hence, our evaluation and analysis results suggest that further research should consider dynamic and workload pattern adaptive approaches to overcome performance degradation from computational kernels with long-term data reuse characteristics and hidden data locality.

• Journal of information and communication convergence engineering
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• 제22권2호
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• pp.139-144
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• 2024

In this study, four types of fall detection systems - designed with YOLOPose, principal component analysis (PCA), convolutional neural network (CNN), and long short-term memory (LSTM) architectures - were developed and compared in the detection of everyday falls. The experimental dataset encompassed seven types of activities: walking, lying, jumping, jumping in activities of daily living, falling backward, falling forward, and falling sideways. Keypoints extracted from YOLOPose were entered into the following architectures: RAW-LSTM, PCA-LSTM, RAW-PCA-LSTM, and PCA-CNN-LSTM. For the PCA architectures, the reduced input size stemming from a dimensionality reduction enhanced the operational efficiency in terms of computational time and memory at the cost of decreased accuracy. In contrast, the addition of a CNN resulted in higher complexity and lower accuracy. The RAW-LSTM architecture, which did not include either PCA or CNN, had the least number of parameters, which resulted in the best computational time and memory while also achieving the highest accuracy.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.391-406
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• 2014

The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. This sensitivity is due to a combination of the underlying Massively Parallel Processing (MPP) execution model present on GPUs and the lack of architectural support to handle irregular memory access patterns. Application performance can be significantly improved by applying memory-access-pattern-aware optimizations that can exploit knowledge of the characteristics of each access pattern. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. To evaluate the effectiveness of our methodology, we report on execution speedup using selected benchmark kernels that cover a wide range of memory access patterns commonly found in GPGPU workloads. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture.

• 전자통신동향분석
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• 제39권1호
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• pp.62-73
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• 2024

Artificial intelligence relies on data-driven analysis, and the data processing performance strongly depends on factors such as memory capacity, bandwidth, and latency. Fast and large-capacity memory can be achieved by composing numerous high-performance memory units connected via high-performance interconnects, such as Compute Express Link (CXL). CXL is designed to enable efficient communication between central processing units, memory, accelerators, storage, and other computing resources. By adopting CXL, a composable computing architecture can be implemented, enabling flexible server resource configuration using a pool of computing resources. Thus, manufacturers are actively developing hardware and software solutions to support CXL. We present a survey of the latest software for CXL memory utilization and the most recent CXL memory emulation software. The former supports efficient use of CXL memory, and the latter offers a development environment that allows developers to optimize their software for the hardware architecture before commercial release of CXL memory devices. Furthermore, we review key technologies for improving the performance of both the CXL memory pool and CXL-based composable computing architecture along with various use cases.