• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.11-19
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• 2010

Register transfer level power macromodeling is well known as a promising technique for accurate and efficient power estimation. This paper proposes effective approaches based on the tablebased method for the RTL power macro-modeling. The new parameter SD, which characterizes the distribution of switching activities for each gate in the circuit, is one of the contributions. The new parameter SD has strong correlation with power consumption. We also propose an accurate table reference method considering the circuit characteristics. The table reference method is applicable for every table-based method and outputs more accurate power value. The experimental results show that the combination of the proposed methods reduces max error 30.36% in the best case, comparing conventional methods. The RMS error is also improved 1.70% in the best case.

• 대한안전경영과학회지
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• 제16권2호
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• pp.111-119
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• 2014

This paper describes the design and implementation of a electromagnetic energy harvesting mechanism and electronic circuit for autonomous emergency call system. This analysis results show the power output of the proposed harvesting mechanism and circuit up to max power output 5V and it can hold up to 65 msec of the power generation and 10msec of the RF transmission. Based on the these testing results, the implementation of autonomous emergency call device without battery power or any external power source is feasible.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.111-112
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• 2011

본 논문에서는 FPGA를 이용하여 SPWM 펄스파형을 구현 했다. 이 파형을 구현하기 위해서 삼각파와 정현파의 비교는 MATLAB을 사용하였고, 비교로 인해서 구해진 파형의 값으로 MAX-PLUS II의 설계를 통해 SPWM 파형을 구현했다. FPGA는 Altera ACEX EP1K100QC208-3N를 모터는 MITSUBISHI AC SERVO MOTOR HC-KFS053를 사용하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.157.6-157
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• 2001

We estimated various neuron functions to construct of engineering neurons, which are the combination of sigmoid, linear, sine, quadric, double/single bended, soft max/minimum functions. These combinations are estimated by the property on the potential surface between the learning points, calculation speed, and learning convergence; because the surface depends on the inference ability of a neuron system; and speed and convergence are depend on the efficiency on the points of engineering applications. After the evaluating discussions, we can select more appropriate combination than original sigmoid function´s, which is single bended function and linear one. The combination ...

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.71-74
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• 2000

The purpose of format conversion is to convert a wide range of personal computer video formats into a target format. Circuits for the conversion have been developed by means of interpolation techniques, such as zero-order interpolation, bilinear interpolation, and bisigmoidal interpolation. This paper proposes a scan converter using cubic splines. The converter was modeled in VHDL on Max+PlusII and implemented with an FPGA chip. The circuit gives much better conversion performance than a scan converter with zero-order or linear interpolation.

• 한국시뮬레이션학회논문지
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• 제9권4호
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• pp.11-23
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• 2000

The purpose of format conversion is to convert a wide range of personal computer video formats into a target format. Circuits for the conversion have been developed by means of interpolation techniques, such as zero-order interpolation, bilinear interpolation, and bisigmoidal interpolation. This paper proposes a scan converter using cubic splines. The converter was modeled in VHDL, simulated on Max+plus Ⅱ , and implemented with an FPGA chip. The circuit gives much better conversion performance than a scan converter with zero-order or linear interpolation techniques according to simulation results and implementation.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2000년도 춘계학술대회 논문집
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• pp.91-95
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• 2000

The purpose of format conversion is to convert a wide range of personal computer video formats to a target format. Circuits for the conversion has been developed by means of interpolation techniques, such as zero-order interpolation, bilinear interpolation, and bisigmoidal interpolation. This paper proposes a scan converter using cubic splines. The converter was modeled in VHDL on Max+Plus II and implemented with an FPGA cpip. The circuit gives much better conversion performance than a scan converter with zero-order or linear interpolation.

• 전기전자학회논문지
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• 제8권1호
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• pp.33-38
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• 2004

다치 논리 패스 게이트는 다치 논리를 구성하기 위한 중요한 소자이다. 본 논문에서는, 뉴런 $MOS({\nu}MOS)$ 임계 게이트를 갖는 2중 패스-트랜지스터 논리를 이용하여 4치 MIN(QMIN)/negated MIN(QNMIN) 게이트 그리고 4치 MAX(QMAX)/negated MAX(QNMAX) 게이트를 설계하였다. DPL은 입력 캐패시턴스의 증가 없이 게이트 속도를 향상 시켰다. 또한 대칭 배열과 2중 전송 특성을 갖는다. 임계 게이트는 ${\nu}MOS$ 다운 리터럴 회로(DLC)로 구성 된다. 제안된 게이트는 다양한 다치 임계 전압을 실현할 수 있다. 본 논문에서, 회로는 3V의 전원 전압을 사용하였고 0.35um N-Well 2-poly 4-metal CMOS 공정의 파라메터를 사용하였으며 모든 모의 실험은 HSPICE를 이용하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.197-199
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• 2002

The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 춘계학술대회
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• pp.61-62
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• 2018

본 논문은 동작하는 3.5 GHz 대역(WiMAX)의 광대역 양면 다이폴 안테나에 대해 연구하였다. 다이폴은 유전체 기판의 양면에 인쇄함으로써 쉽게 구현될 수 있고 능동회로와의 접속에 적합하다. 광대역 특성을 얻기 위해 다이폴 안테나의 모양은 두꺼운 직사각형 모양으로 하였다. $50{\Omega}$ 마이크로스트립 급전 선로에 정합 되도록 배열 급전회로와 밸런을 설계하였다. 시뮬레이션을 통해 3.4~3.7 GHz 대역의 안테나를 설계하고 반사손실, 이득, 방사패턴 등의 안테나 특성을 확인하였다. 시뮬레이션 결과 3.5GHz 대역의 최대이득은 5.5 dBi이고 VSWR이 2 미만인 대역폭은 약 1GHz이다.