• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.483-484
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• 2010

$3{\times}3$ 매트릭스 컨버터(matrix converter)는 3상 입력 전원이 3상 부하에 직접 연결되는 에너지 변환 장치이다. 기존의 AC-DC-AC 전력변환 장치와는 달리 매트릭스 컨버터는 직류단의 전해 커패시터가 존재하지 않기 때문에 불평형의 입력전원은 왜곡된 출력전류를 발생시킨다. 왜곡된 출력전류를 보상하기 위해 본 논문에서는 신경망 기반 전류 보상기를 제안한다. 제안된 기법의 타당성을 시뮬레이션을 통해 증명한다.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1043-1044
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• 2006

본 논문은 전동기의 일정한 공극자속과 전동기에 유입되는 무효전력을 이용한 매트릭스 컨버터 구동장치의 새롭고 간단한 센서리스 기법을 제안한다. 저속의 센서리스 성능 향상을 위해 정류지연, 스위칭장치들의 턴-온, 턴-오프시간 그리고 스위칭장치의 온-상태에서 전압강하와 같은 매트릭스 컨버터의 비선형성을 PQR 전력변환을 이용하여 모델링하고 기준 전류제어기법을 이용하여 보상한다. 3 kW급의 매트릭스 컨버터 구동시스템에 적용하여 제안된 센서리스 기법의 타당성을 검증한다.

• Proceedings of the KIPE Conference
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• 2004.11a
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• pp.37-40
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• 2004

본 논문에서는 캐리어(Carrier)를 이용한 매트릭스 컨버터(Matrix Converter)의 전압 변조 방법을 제안한다. 출력 상전압에 적절한 옵셋(Offset) 전압을 더하고, 캐리어 파형의 기울기를 적절히 제어함으로써 입력 전류를 역율 1의 정현파로 제어하면서 동시에 출력 전압의 합성이 가능하다. 이 방법은 기존의 매트릭스 컨버터 전압 변조 방법인 SVPWM과 동일한 스위칭 패턴을 나타내지만, 그 구현은 훨씬 간단한다. 또한 기존의 전압형 인버터(Voltage Source Inverter, VSI)에서 발전된 2상/3상 변조, 과변조(Over Modulation) 등의 개념을 유사하게 적용 할 수 있어 그 활용도가 매우 높다. Matlab/Simulink를 이용한 시뮬레이션 결과를 통해 제안된 방법의 타당성을 검증하였다.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.190-192
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• 2008

매트릭스 컨버터(Matrix Converter:MC)는 기본적으로 9개의 양방향 스위치를 이용한 전력변환장치이다. 입력 전압의 크기에 따라 일정 범위 내의 전압을 합성할 수 있으며, 다이오드 정류기를 이용하는 인버터에 비해 입력전류를 정현파로 만들 수 있는 장점을 가지고 있다. 다수의 스위치를 이용하여 출력전압을 합성하기 때문에 제어가 복잡하다는 단점이 있으나, 반대로 여러 가지 방법으로 전압을 합성할 수 있는 가능성과 회로 구성의 확장 가능성이 크다는 장점도 있다. 본 논문에서는 입력 전압의 순시적인 선간전압을 이용한 새로운 공간 벡터 변조(Space Vector Modulation: SVM)방법을 제안하고, 기존 SVM과 동일한 구현 가능성 및 새로운 유사 멀티레벨(Multi-level) SVM으로의 확장성을 보인다. 유사 멀티레벨 SVM을 사용하였을 경우 출력 전류의 리플이 감소하고 고조파 특성이 개선됨을 Matlab 시뮬레이션을 통해 검증한다.

• Journal of Power Electronics
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• v.11 no.3
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• pp.327-334
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• 2011

Single-phase power factor correction (PFC) converter circuits are non-linear systems due to the contribution of their multiplier. This non-linearity causes difficulties in analysis and design. Models that reduce the system to a linear system involve considerable approximation, and produce results that are susceptible to instability problems. In this paper a piecewise affine (PWA) system is introduced for describing the nonlinear averaged model. Then robust output feedback controllers are established in terms of the linear matrix inequality (LMI). Simulation and experiments results show the effectiveness of the proposed control method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.3
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• pp.627-631
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• 2009

This paper presents a novel current steering cell matrix DAC(digital-to-analog converter) architecture to reduce decoder area. The current cell matrix of a existing architecture is selected by columns and lows thermometer code decoder of input bits. But The current cell matrix of a proposal architecture is divided 2n by the thermometer code decoder of upper input bits and are selected by the thermometer code decoder of middle and lower input bits. Because of this configuration, decoder numbers have increased. But the gate number that composed of decoder has decreased. In case of the designed 8 bit current steering cell matrix DAC, the gate number of decoder has decreased by about 55% in comparison with a existing architecture.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.376-378
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• 2008

A new family of single-phase Z-source ac-ac converter(SZAC) based on single-phase matrix converter (SPMC) is proposed in this paper. Compared to conventional Z-source ac-ac converter, the proposed SZAC has unique feature: providing a wide range of output ac voltage with buck/boost in-phase (maintaining phase angle) and buck/boost out-of-phase (reversing phase angle) operation. A new commutation strategy is used to eliminate voltage spikes on switches. The operating principle of the proposed SZAC is presented. Analysis and experimental results are also presented.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.50-59
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• 1998

This paper describes a 3.3V 8bit CMOS digital to analog converter (DAC) with two state current cell metrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allow the designed DAC to reduce hot only a complexity of decoding logics, but also a number of wider swing cascode curent mirros. The designed DAC with an active chip area of 0.8 mm$_{2}$ is fabricated by a 0.8 .mu.m CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are6ns, 15ns, and a less than .+-.0.8/.+-.0.75 LB, respectively. The designed DAC is fully operational for the power supply down to 2.0V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3V is measured to be 34.5mW.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1456-1467
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• 2015

This paper presents a novel close-loop control scheme based on small signal modeling and weighted composite voltage feedback for a three-phase input and single-phase output Matrix Converter (3-1MC). A small non-polar capacitor is employed as the decoupling unit. The composite voltage weighted by the load voltage and the decoupling unit voltage is used as the feedback value for the voltage controller. Together with the current loop, the dual-loop control is implemented in the 3-1MC. In this paper, the weighted composite voltage expression is derived based on the sinusoidal pulse-width modulation (SPWM) strategy. The switch functions of the 3-1MC are deduced, and the average signal model and small signal model are built. Furthermore, the stability and dynamic performance of the 3-1MC are studied, and simulation and experiment studies are executed. The results show that the control method is effective and feasible. They also show that the design is reasonable and that the operating performance of the 3-1MC is good.

• Journal of Power Electronics
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• v.19 no.1
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• pp.89-98
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• 2019

This paper analyzes the input side performance of a conventional three-phase to single-phase matrix converter (3-1MC). It also presents the input-side waveform quality under this topology. The suppression of low-frequency input current harmonics is studied using the 3-1MC plus capacitance compensation unit. The constraint between the modulation function of the output and compensation sides is analyzed, and the relations among the voltage utilization ratio and the output compensation capacitance, filter capacitors and other system parameters are deduced. For a 3-1MC without large-capacity energy storage, the system performance is susceptible to input voltage imbalance. This paper decouples the inner current of the 3-1MC using a Lyapunov function in the input positive and negative sequence bi-coordinate axes. Meanwhile, the outer loop adopts a voltage-weighted synthesis of the output and compensation sides as a cascade of control objects. Experiments show that this strategy suppresses the low-frequency input current harmonics caused by input voltage imbalance, and ensures that the system maintains good static and dynamic performances under input-unbalanced conditions. At the same time, the parameter selection and debugging methods are simple.