• ETRI Journal
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• v.37 no.3
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• pp.523-532
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• 2015

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip-chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine-pitch solder bumping has been widely studied. In this study, high-volume solder-on-pad (HV-SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are $28.3{\mu}m$, $31.7{\mu}m$, and $26.3{\mu}m$, respectively. It is expected that the HV-SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine-pitch flip-chip bonding.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.942-945
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• 1999

In this work, we proposed Proper etching algorithm for ultra-large scale integrated circuit device and simulated etching process using the proposed algorithm in the case of ICP (inductive coupled plasma) 〔1〕source. Until now, many algorithms for etching process simulation have been proposed such as Cell remove algorithm, String algorithm and Ray algorithm. These algorithms have several drawbacks due to analytic function; these algorithms are not appropriate for sub 0.1 ${\mu}{\textrm}{m}$ device technologies which should deal with each ion. These algorithms could not present exactly straggle and interaction between Projectile ions and could not consider reflection effects due to interactions among next projectile ions, reflected ions and sputtering ions, simultaneously In order to apply ULSI process simulation, algorithm considering above mentioned interactions at the same time is needed. Proposed algorithm calculates interactions both in plasma source region and in target material region, and uses BCA (binary collision approximation4〕method when ion impact on target material surface. Proposed algorithm considers the interaction between source ions in sheath region (from Quartz region to substrate region). After the collision between target and ion, reflected ion collides next projectile ion or sputtered atoms. In ICP etching, because the main mechanism is sputtering, both SiO$_2$ and Si can be etched. Therefore, to obtain etching profiles, mask thickness and mask composition must be considered. Since we consider both SiO$_2$ etching and Si etching, it is possible to predict the thickness of SiO$_2$ for etching of ULSI.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.389-395
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• 2005

The etching technology of the high aspect ratio contact(HARC) is necessary at the critical contact processes of semiconductor devices. Etching the $SiO_{2}$ contact hole with the sub-micron design rule in manufacturing VLSI devices, the unexpected phenomenon of 'profile tilting' or 'bottom distortion' is often observed. This makes a short circuit between neighboring contact holes, which causes to drop seriously the device yield. As the aspect ratio of contact holes increases, the high C/F ratio gases, $C_{4}F_{6}$, $C_{4}F_{8}$ and $C_{5}F_{8}$, become widely used in order to minimize the mask layer loss during the etching process. These gases provide abundant fluorocarbon polymer as well as high selectivity to the mask layer, and the polymer with high sticking yield accumulates at the top-wall of the contact hole. During the etch process, many electrons are accumulated around the asymmetric hole mouth to distort the electric field, and this distorts the ion trajectory arriving at the hole bottom. These ions with the distorted trajectory induce the deformation of the hole bottom, which is called 'profile tilting' or 'bottom distortion'. To prevent this phenomenon, three methods are suggested here. 1) Using lower C/F ratio gases, $CF_{4}$ or $C_{3}F_{8}$, the amount of the Polymer at the hole mouth is reduced to minimize the asymmetry of the hole top. 2) The number of the neighboring holes with equal distance is maximized to get the more symmetry of the oxygen distribution around the hole. 3) The dual frequency plasma source is used to release the excessive charge build-up at the hole mouth. From the suggested methods, we have obtained the nearly circular hole bottom, which Implies that the ion trajectory Incident on the hole bottom is symmetry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.502-502
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• 2007

Current thin film process using memory device fabrication process use expensive processes such as manufacturing of photo mask, coating of photo resist, exposure, development, and etching. However, direct printing technology has the merits about simple and cost effective processes because inks are directly injective without mask. And also, this technology has the advantage about fabrication of fine pattern line on various substrates such as PCB, FCPB, glass, polymer and so on. In this work, we have fabricated the fine and thick metal pattern line for the electronic circuit board using metal ink contains Ag nano-particles. Metal lines are fabricated by two types of printing methods. One is a conventional printing method which is able to quick fabrication of fine pattern line, but has various difficulties about thick and high resolution DPI(Dot per Inch) pattern lines because of bulge and piling up phenomenon. Another(Second) methods is sequential printing method which has a various merits of fabrication for fine, thick and high resolution pattern lines without bulge. In this work, conductivities of metal pattern line are investigated with respect to printing methods and pattern thickness. As a result, conductivity of thick pattern is about several un.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.55-65
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• 2020

The use of underfill materials in semiconductor packages is not only important for stress relieving of the package, but also for improving the reliability of the package during shock and vibration. However, in recent years, as the size of the package becomes larger and very thin, the use of the underfill shows adverse effects and rather deteriorates the reliability of the package. To resolve these issues, we developed the package using a solid epoxy material to improve the reliability of the package as a substitute for underfill material. The developed solid epoxy was applied to the package of the application processor in smart phone, and the reliability of the package was evaluated using thermal cycling reliability tests and numerical analysis. In order to find the optimal solid epoxy material and process conditions for improving the reliability, the effects of various factors on the reliability, such as the application number of solid epoxy, type of PCB pad, and different solid epoxy materials, were investigated. The reliability test results indicated that the package with solid epoxy exhibited higher reliability than that without solid epoxy. The application of solid epoxy at six locations showed higher reliability than that of solid epoxy at four locations indicating that the solid epoxy plays a role in relieving stress of the package, thereby improving the reliability of the package. For the different types of PCB pad, NSMD (non-solder mask defined) pad showed higher reliability than the SMD (solder mask defined) pad. This is because the application of the NSMD pad is more advantageous in terms of thermomechanical stress reliability because the solderpad bond area is larger. In addition, for the different solid epoxy materials with different thermal expansion coefficients, the reliability was more improved when solid epoxy having lower thermal expansion coefficient was used.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04a
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• pp.129-132
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• 2000

The PDP(Plasma Display Panel) barrier rib material on the glass substrate was patterned for fabrication of the PDP cell using Nd:YAG laser(1064 nm) which can generate the second(532 nm) and forth(266 nm) harmonic wave by HGM(harmonic generation modules). At a scan speed of 20 ${\mu}m/s$ with the second harmonic wave(532 nm) of Nd:YAG laser, the etching threshold laser fluence of the PDP material was 6.5 $mJ/cm^2$ and a sample(thickness = 180 ${\mu}m$) on the glass substrate was removed clearly at a laser fluence of 19.5 $mJ/cm^2$. In order to increase the throughput of the fabrication we divided a single-beam into multi-beams by using a metal mask between the sample and the focusing lens. As a result, 10 lines of PDP cell were formed by one laser beam scanning at a scan speed of 200 ${\mu}m/s$ and a laser fluence of 2.86 $J/cm^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.250-250
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• 2009

The fabricated the nanostructural patterns on the surface of SiN antireflection layer of polycrystalline Si solar cell using anodic aluminum oxide (AAO) masks in an inductively coupled plasma(ICP) etching process. The AAO nanopattern mask has the hole size of about 70~75nm and lattice constant of 100~120nm. The transferred nano-patterns were observed by the scanning electron microscope (SEM). The voltage of patterned Si solar cell enhanced.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.414-414
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• 2009

나노스피어 리소그래피는 기존의 리소그래피 방법에 비해 나노 크기 패턴을 제작하는데 공정이 간단하며 재현성있게 대면적에 패터닝이 가능하다는 장점이 있다. 본 연구에서는 Vertical LED(V-LED)의 External quantum efficiency 향상을 위하여 나노스피어 리소그래 피를 이용하여 V-LED의 n-GaN 표면을 패터닝을 하였다. n-GaN 위에 Sputter를 이용하여 $SiO_2$를 증착 후 나노스피어를 스핀 코팅을 이용하여 단일막을 형성하였다. 그 후, 반응성 이온 식각 장치를 이용하여 나노스피어의 크기를 조절하고 $SiO_2$층을 식각하였다. 다음과 같은 공정 후 $SiO_2$층을 Mask층으로 하여 n-GaN 표면을 식각하였다. 실험 결과 나노스피어 리소그래피를 이용하여 V-LED의 External quantum efficiency 향상을 위한 n-GaN 표면의 패턴 제작이 가능함을 확인할 수 있었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.419-420
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• 2009

The authors fabricated the nanostructural patterns on the surface of SiN antireflection layer of polycrystalline Si solar cell and the surface of crystalline Si wafer using anodic aluminum oxide (AAO) masks in an inductively coupled plasma(ICP) etching process. The AAO nanopattern mask has the hole size of about 70~80nm and an ave rage lattice constant of 100nm. The transferred nano-patterns were observed by the scanning electron microscope (SEM) and the enhancement of solar cell efficiency will be presented.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.231-236
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• 2005

To investigate the electrical properties at the single grainboundary of ZnO varistors, micro-electrodes were fabricated on the surface which was polished and thermally etched. Our micro-electrode had 2000 $\AA$ silicon nitride layer between micro-electrode and ZnO surface. This layer was deposited by PECVD and etched by RIE after photoresistor pattering process using by mask 1. The metal patterning of micro-electrodes used lift-off method. We found that the breakdown voltage of single grainboundary is about 3.5∼4.2 V at 0.1 mA on I-V curves. Also, capacitance-voltage measurement at single grainboundary gave several parameters( $N_{d}$, $N_{t}$, $\Phi$$_{b}$, t) which were related with grainboundary.ary.