• Proceedings of the IEEK Conference
• /
• 2001.09a
• /
• pp.465-468
• /
• 2001

MPEG-4 Parametric Coding 중 저 비트율로 음성신호를 부호화하는 HVXC(Harmonic Vector excitation Ending)의 복호화 모듈인 LSP 합성필터와 무성음 합성부, 유성음 합성부를 VHDL을 이용하여 구현하였다. MPEG-4 HVXC의 복호화 과정은 코드북을 이용하여 LSP 계수, VXC signal, 그리고 Spectral Envelop이 복호화 되어 각각 LSP 역필터, 무성음과 유성음 합성단을 통과하여 LPC계수와 유,무성음 여기신호로 변환된 후 LPC 합성필터링 과정을 거쳐 최종적으로 음성신호를 출력시킨다. LSP inverse filter에서 사용되는 cosine함수값을 위하여 Table based Approximation을 이용하여 적은 양의 Table 값을 사용하여 정확하고 고속의 cosine 연산을 수행하였다. VXC 복호화 과정에서는 신호의 중복성을 제거하는 Hidden Address in LSH 방법을 사용하여 코드북의 크기를 줄였다. 유성음 합성단에서는 IFFT 모듈을 이용하여 연산속도를 증가 시켰다. 최종적으로 위와 같이 구현된 시스템을 Simulation을 통해 Software 검증을 하였다.

• Proceedings of the IEEK Conference
• /
• 2003.11a
• /
• pp.251-254
• /
• 2003

본 논문의 목표는 디지털방송과 인터넷의 융합에 따른 MPEG-2/4/7 방송 및 인터넷 콘텐츠을 비롯한 게임등과 같은 다양한 멀티미디어 서비스를 제공하기 위한 차세대 지능형 고품질 홈 엔터테인먼트 시스템 Platform 개발이다. 디지털 방송과 데이터방송 수신이 가능한 Set-Top Box기능, 수신된 방송의 저장 및 재생이 가능한 PDR 기능, MPEG-2 형식을 MPEG-4 형식으로 변환하는 Transcoding 기능, VOD 서비스를 제공하기 위한 Streaming 기능 등을 지원할 수 있는 시스템의 구조를 설계하였다. 이러한 지능형 고품질 서비스를 지원하기 일해 고성능 시스템이 필요하다. 시스템 제어를 위한 CPU 로는 PMC-Sierra사의 MIPS Architecture에 기반을 둔 RM5231 을 채택하고, MPEC-4 Decoding, BIFS Presentation Engine과 Streaming 서비스와 MPEC-7 Metadata Generator/Parser 을 위해 ARM Architecture에 기반을 둔 Intel80200 Processor 를 채택하였다. 또한, 디지털방송을 위한 MPEC-2 Decoder Chip 인 Teraloglc 사의 TL811 System Controller 와 TL851 Graphics& Display Processor 를 채택하였다. 개발된 시스템을 테스트하기 위하여 DVB-MHP Server와 MPEG-4 IP Streaming Server 를 구축하여 디지털 방송과 Streaming 서비스를 테스트하였다.

• ETRI Journal
• /
• v.27 no.5
• /
• pp.491-496
• /
• 2005

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction-level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.

• The Journal of the Acoustical Society of Korea
• /
• v.21 no.3
• /
• pp.237-244
• /
• 2002

In this paper we mention the optimization of MPEG-4 VM (Moving Picture Expert Group-4 Verification Model) GA (General Audio) AAC (Advanced Audio Coding) encoder and the design of the decoder for PDA (Personal Digital Assistant) using MPEG-4 VM source. We profiled the VMC source and several optimization methods have applied to those selected functions from the profiling. Intel Pentium III 600 MHz PC, which uses windows 98 as OS, takes about 20 times of encoding time compared to input sample running time, with additional options, and about 10 times without any option. Decoding time on PDA was over 35 seconds for the 17 seconds input sample. After optimization, the encoding time has reduced to 50% and the real time decoding has achieved on PDA.

• Proceedings of the KIEE Conference
• /
• 2005.10b
• /
• pp.361-363
• /
• 2005

본 논문에서는 MPEG-4 Version2 Audio 표준에 근거하여 낮은 연산부담을 갖는 독자적인 엘고리즘을 적용한 MPEG-4 BSAC Audio 디코더를 개발하였다. 개발된 BSAC 디코더는 32bit RISC 구조를 갖는 Intel Xscale Processor 기반 시스템에 최적화하여 구현 및 평가를 수행하였다. 수행속도 증가 및 연산 정밀도 향상을 위해 각 기능 블록별 기능 및 구현 원리 연구와 32 bit 연산 구조를 파악하여, 이를 고정소수점 연산 구조로 구현함으로써 성능을 향상시켰다. 유한비트에 따른 오차 영향을 최소화하기 위해 데이터의 표현 범위에 대한 연구를 통해 근사한 오차를 최소화 하여 연산 정밀도를 향상 시키고자 하였다. 비선형 양자화기 및 filter bank 등 상대적으로 높은 연산 부담을 갖는 기능 블록은 Table look-up, 보간법, 지수연산 제거, pre/post scrambling 기법 등을 적용하여 최적화 하였다. 최종적으로 개발된 BSAC 디코더는 32 bit 연산 구조의 X-scale 프로세서를 탑재한 Development Board와 WindowsCE OS로 구성된 타겟 system에 이식하여 performance 평가하였으며, 높은 연산 정밀도 및 다른 수행속도를 확인할 수 있었다. 주관적인 청각 평가에서도 MPEG-4 reference 디코더와의 음원의 차이가 거의 없음을 확인하였다.

• Journal of Sensor Science and Technology
• /
• v.25 no.6
• /
• pp.388-393
• /
• 2016

MPEG-V(ISO/IEC 23005) standardizes normative sensory effects metadata and sensory devices command for adapting the sensory effects between the virtual world and the real world. MPEG-V(Virtual) standardization has been carried out by 3DG(Dimensional Graphics) ad-hoc group inside MPEG Working Group(ISO IEC JTC1/SC29/WG11). For the scent effect, one of the sensory effects within MPEG-V, we proposed an olfactory interaction model including electronic nose and scent display to the ad-hoc group. Recently, we proposed types and elements related to the electronic nose as a sensor defined in MPEG-V standard for olfactory interaction. At the 114th MPEG meeting, the types and elements were consequently reflected on MPEG-V CD(Committee Draft) 4th edition. In this paper, we implement an electronic nose system applicable to MPEG-V standard by using MPEG-V schema, encoder, and decoder in order to assess their adequacy.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.11
• /
• pp.29-36
• /
• 2003

In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• The Journal of the Acoustical Society of Korea
• /
• v.26 no.5
• /
• pp.214-219
• /
• 2007

This paper proposes a new IFFT(Inverse Fast Fourier Transform) algorithm, which is proper for IMDCT(Inverse Modified Discrete Cosine Transform) of MPEG-2 AAC(Advanced Audio Coding) decoder. The $2^n$(N-point) type IMDCT is the most powerful among many IMDCT algorithms, however it includes IFFT that requires many calculation cycles. The IFFT used in $2^n$(N-point) type IMDCT employ the bit-reverse data arrangement of inputs and N/4-point complex IFFT to reduce the calculation cycles. We devised a new data arrangement method of IFFT input and $N/4^{n+1}$-type IFFT and thus we can reduce multiplication cycles, addition cycles, and ROM size.

• Smart Media Journal
• /
• v.1 no.1
• /
• pp.27-35
• /
• 2012

In this paper, the performance analysis for multimedia video codec(MPEG-4, H.264) on on-chip network communication architecture is presented. The On-Chip Network (OCN) is the new communication architecture of multimedia SoC design that overcomes the limits of On-Chip Bus architecture by providing higher data traffic bandwidth, reusability and higher scalability. We compared the performance of MPEG-4, H.264 decoder based on-chip network and AMBA on-chip bus. Experimental results show that the performance of MPEG-4, H.264 based on on-chip network is improved over 33~56% compared to the design based on AMBA on-chip bus.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.1B
• /
• pp.117-124
• /
• 2004

With MPEG-4 3D mesh coding(3DMC), the problem of the need of a wide bandwidth can be solved to store and transmit 3D information because of its high compression rate. And to realize the 3D information service with broadcasting or internet, one needs to transmit not only the 3D contents but also the 3D player. Therefore, in this paper we implement a 3D player based on MPEG-4 using a java language. A well-known java language employed in this paper provides the player with a wider range of applications, for example, when the O/S or the platform are different, due to its properties of scalability and universality. The implemented player which has functions (translation, rotation, etc) that can manipulate contents decodes the 3D contents and displays them. In addition, the player has a network function that receives a 3D content from the server. This paper explains the architecture and characteristics of the player and shows its simulation results.