• The KIPS Transactions:PartB
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• v.12B no.6 s.102
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• pp.637-646
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• 2005

Most of the multimedia contents for DBM services art provided as MPEG-2 bit streams. However, they have to be transcoded to H.264 bit streams for practical services because the standard video codec for DMB is H.264. The existing transcoder architecture is Cascaded Pixel-Domain Transcoding Architecture, which consists of the MPEG-2 dacoding phase and the H.264 encoding phase. This architecture can be easily implemented using MPEG-2 decoder and H.264 encoder without source modifying. However. It has disadvantages in transcoding time and DCT-mismatch problem. In this paper, we propose two kinds of transcoder architecture, DCT-OPEN and DCT-CLOSED, to complement the CPDT architecture. Although DCT-OPEN has lower PSNR than CPDT due to drift problem, it is efficient for real-time transcoding. On the contrary, the DCT-CLOSED architecture has the advantage of PSNR over CPDT at the cost of transcoding time.

• Journal of Korea Multimedia Society
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• v.9 no.3
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• pp.296-306
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• 2006

We proposed the algorithm for the quantization noise reduction based on variable filter adaptive to edge signal in MPEG postprocessing system. In our algorithm, edge map and local modulus maxima in the decoded images are obtained by using 2D Mallat wavelet tilter. And then, blocking artifacts in inter-block are reduced by Gaussian LPF that is variable to filtering region according to edge map. Ringing artifacts in intra-block are reduced by 2D SAF according to local modulus maxima. Experimental results show that the proposed algorithm was superior to the conventional algorithms as regards PSNR, which was improved by 0.04-0.20 dB, and the subjective image quality.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.355-355
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• 2002

In this paper, we designed a FPU(floating point unit) that it is very important and requires of high density when digital audio is designed. Almost audio system must support the multi-channel and required for high quality. A floating point arithmetic function in MPEG-2 AAC that implemented by hardware is able to realtime decoding when DSP realization. The reason is that MPEG-2 AAC is compatible to the Audio field of MPEG-4 and afterwards. We designed a FPU by hardware to increase the speed of a floating point unit with much calculation part in the MPEG-2 AAC Decoder. A FPU is composed of a multiplier and an adder. A multiplier used the Radix-4 Booth algorithm and an adder adopted 1's complement method for speed up. A form of a floating point unit has 8bit of exponent part and 24bit of mantissa. It's compatible with the IEEE single precision format and adopted a pipeline architecture to increase the speed of a processor. All of sub blocks are based on ISO/IEC 13818-7 standard. The algorithm is tested by C language and the design does by use of VHDL(VHSIC Hardware Description Language). The maximum operation speed is 23.2MHz and the stable operation speed is 19MHz.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.11a
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• pp.97-100
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• 2009

The paper describes synchronization schemes for scalable video coding signals over the DVB-S2 network. The MPEG-4 SVC signals include a base layer signal and an enhancement layer signal. They are packetized into MPEG-2 transport streams and transmitted on separate RF channels through the DVB-S2 system. The DVB-S2 receiver is required to synchronize each layer signal together to recover the full pictures. Some new schemes to synchronize two. layered SVC signals in MPEG-4 SVC decoder are proposed and analyzed.

• Journal of Digital Contents Society
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• v.9 no.3
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• pp.371-377
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• 2008

Recently the performance of GPU is increasing much faster compared to GPU and GPU is used for various application programs. In this paper, MPEG-2 Decoder is implemented based on a GPU programming language, CG. The proposed methodology is to perform block rendering with texture data according to video standard with very high parallelism by using the pipeline of GPU which is a stream processing structure. To reduce the data bandwidth between system memory and GPU, local memory is used for graphic card. According to the experiment, the proposed scheme shows performance improvement by more than 2 times compared to CPU based scheme.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.1
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• pp.113-118
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• 2001

In this paper, we implement modules of the MPEG-2 AAC decoder using VHDL. Tools of Huffman decoder, inverse quantizer and high-density filter bank which are necessary for the AAC decoder. We designed the high speed Huffman decoder using the method of octal tree search algorithm, and reduced computational time of filter bank using IFFT. Also, we use table of computation result for an exponential calculation of Inverse quantizer in fixed-point hardware, and reduced the size of table using linear interpolation. Modules implemented by hardware through optimization work in real time at low clock frequency are possible to reduce the system size.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.57-62
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• 2011

In this paper, an efficient architecture for MFVLD(Multi-Format Variable Length Decoder) which can process H.264, MPEG-2, MPEG-4, AVS, VC-1 bitstream is proposed. The proposed MF-VLD is designed to be adapted to the MPSOC (Multi-processor System on Chip) architecture, uses bit-plane algorithm for the processing of inverse quantized data to reduce the width of AHB bus. External SDRAM is used to minimize the internal memory size. In this architecture, the adding or removing each variable length decoder can be easily done by using multiplexor. The designed MF-VLD can be operated in 200MHz at 0.18um process. The gate size is 657K gate and internal memory size is 27Kbyte.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.2
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• pp.138-148
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• 2001

Digital Video (DV) coding standards for digital video cassette recorder are based mainly on DCT and variable length coding. DV has low hardware complexity but high compressed bit rate of about 26 Mb/s. Thus, it is necessary to encode video with low complex video coding at the studios and then transcode compressed video into MPEG-2 for video-on-demand system. Because these coding methods exploit DCT, transcoding in the DCT domain can reduce computational complexity by excluding duplicated procedures. In transcoding DV into MPEC-2 intra coding, multiplying matrix by transformed data is used for 4:1:1-to-4:2:2 chroma format conversion and the conversion from 2-4-8 to 8-8 DCT mode, and therefore enables parallel processing. Variance of sub block for MPEG-2 rate control is computed completely in the DCT domain. These are verified through experiments. We estimate motion hierarchically using DCT coefficients for transcoding into MPEG-2 inter coding. First, we estimate motion of a macro block (MB) only with 4 DC values of 4 sub blocks and then estimate motion with 16-point MB using IDCT of 2$\times$2 low frequencies in each sub block, and finish estimation at a sub pixel as the fifth step. ME with overlapped search range shows better PSNR performance than ME without overlapping.

• Journal of Broadcast Engineering
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• v.15 no.2
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• pp.205-216
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• 2010

In this paper, a method of MPEG-2 Transport Stream (TS) multiplexing for Ultra HDTV (UHDTV) and its design and implementation as a SW tool is described. In practice, UHD video may be divided into several HD videos and each video is encoded in parallel. Therefore, it is necessary to synchronize and multiplex multiple bitstreams encoding each HD video for transmitting and storing UHD video. In this paper, it is assumed that 4 HD videos partitioning a UHD spatially are encoded as H.264/AVC and two 5.0 channel audios are encoded by AC-3. Therefore, 4 H.264/AVC elementary streams (ESs) and 2 AC-3 ESs is mainly considered in the TS multiplexing of UHD. For the carriage of H.264/AVC and AC-3 over MPEG-2 TS, PES packetization and TS multiplexing are designed and implemented based on the extended specification of the MPEG-2 Systems and ATSC (Digital audio compressed standard), respectively. The implemented UHD TS multiplexing tool emulates real time HW operation in the time unit corresponding to the duration of one TS packet transmission in a given TS rate. In particular, in order to satisfy the timing model, the buffers defined in the TS System Target Decoder (T-STD) are monitored and their statuses are considered in the scheduling of TS multiplexing. For UHD multiplexing, two kinds of multiplexing structures, which are UHD re-multiplexing and UHD program multiplexing, are implemented and their strength and weakness are investigated. The developed UHD TS multiplexing tool is tested and verified in terms of the syntax and semantics conformance and functionalities by using a commercial analyzer and real-time presentation tools.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.251-254
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• 2003

본 논문의 목표는 디지털방송과 인터넷의 융합에 따른 MPEG-2/4/7 방송 및 인터넷 콘텐츠을 비롯한 게임등과 같은 다양한 멀티미디어 서비스를 제공하기 위한 차세대 지능형 고품질 홈 엔터테인먼트 시스템 Platform 개발이다. 디지털 방송과 데이터방송 수신이 가능한 Set-Top Box기능, 수신된 방송의 저장 및 재생이 가능한 PDR 기능, MPEG-2 형식을 MPEG-4 형식으로 변환하는 Transcoding 기능, VOD 서비스를 제공하기 위한 Streaming 기능 등을 지원할 수 있는 시스템의 구조를 설계하였다. 이러한 지능형 고품질 서비스를 지원하기 일해 고성능 시스템이 필요하다. 시스템 제어를 위한 CPU 로는 PMC-Sierra사의 MIPS Architecture에 기반을 둔 RM5231 을 채택하고, MPEC-4 Decoding, BIFS Presentation Engine과 Streaming 서비스와 MPEC-7 Metadata Generator/Parser 을 위해 ARM Architecture에 기반을 둔 Intel80200 Processor 를 채택하였다. 또한, 디지털방송을 위한 MPEC-2 Decoder Chip 인 Teraloglc 사의 TL811 System Controller 와 TL851 Graphics& Display Processor 를 채택하였다. 개발된 시스템을 테스트하기 위하여 DVB-MHP Server와 MPEG-4 IP Streaming Server 를 구축하여 디지털 방송과 Streaming 서비스를 테스트하였다.