• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1152-1155
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• 1995

An analytic model for the optimum design of the power MOSFET considering the degradation of the breakdown voltage by the three dimensional effect is proposed. The proposed method gives the optimum design parameters such as the lateral radius of window curvature and the doping concentration of the epi-layer, which does not minimize the on-resistance but also maintains the required breakdown voltage. The analytical results are verified by the quasi 3D simulation tools, MEDICI, and it is found that the proposed method may be a good guideline for the design of power MOSFET.

• 센서학회지
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• 제26권2호
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• pp.79-84
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• 2017

The drain current of the SB MOSFET was analytically modeled by an equation composed of thermionic emission and tunneling with consideration of the image force lowering. The depletion region electron concentration was used to model the channel electron concentration for the tunneling current. The Schottky barrier width is dependent on the channel electron concentration. The drain current is changed by the gate oxide thickness and Schottky barrier height, but it is hardly changed by the doping concentration. For a GaN SB MOSFET with ITO source and drain electrodes, the calculated threshold voltage was 3.5 V which was similar to the measured value of 3.75 V and the calculated drain current was 1.2 times higher than the measured.

• 전자공학회논문지A
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• 제31A권1호
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• pp.77-83
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• 1994

Characteristics of hot-electron-induced degradation by AC, DC was investigated for p-MOSFET's(W/L=25/l$\mu$m) with sub-10nm RTP-CVD gate oxides. It was confirmed that the surface channel p-MOSFET of a thinner gate oxide shows less degradation. Mechanisms for this effect were analyzed using a simple MOS Device degradation model. It was found that the number of generated electron traps(fixed charge) is determined by the amount of peak gate current, dependent of the gate oxide thickness, and the major cause of the smaller degradation in the thinner gate oxide devices is the lower hot electron trapping carriers.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1989년도 추계학술대회 논문집 학회본부
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• pp.131-135
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• 1989

Hot electron simulation of silicon using Monte Carlo method was carried out to investigate impact ionization characteristics near the drain of MOSFET's at 77 and 300K. We successfully characterized drift velocity and impact ionization at 77 and 300K employing a simplified energy band structure and phonon scattering mechanisms. Woods' soft energy threshold model was introduced to the Monte Carlo simulation of impact ionization, and good agreement with reported experimental results was resulted by employing threshold energy of 1.7 eV. It is suggested that the choice of the critical angle between specular reflection and diffusive scattering of surface roughness scattering may be important in determining the impact ionization charateristics of Monte Carlo simulation near the drain of MOSFET's.

• Journal of Power Electronics
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• 제19권2호
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• pp.591-601
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• 2019

With the development of renewable energy, grid-connected inverter technology has become an important research area. When compared with traditional silicon IGBT power devices, the silicon carbide (SiC) MOSFET shows obvious advantages in terms of its high-power density, low power loss and high-efficiency power supply system. It is suggested that this technology is highly suitable for three-phase AC motors, renewable energy vehicles, aerospace and military power supplies, etc. This paper focuses on the SiC MOSFET behaviors that concern the parasitic component influence throughout the whole working process, which is based on a three-phase grid-connected inverter. A high-speed model of power switch devices is built and theoretically analyzed. Then the power loss is determined through experimental validation.

• 한국전기전자재료학회논문지
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• 제36권2호
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• pp.129-135
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• 2023

An analytical threshold voltage model is presented to observe the change in threshold voltage shift ΔV_th of a junctionless double gate MOSFET using ferroelectric-metal-SiO₂ as a gate oxide film. The negative capacitance transistors using ferroelectric have the characteristics of increasing on-current and lowering off-current. The change in the threshold voltage of the transistor affects the power dissipation. Therefore, the change in the threshold voltage as a function of theferroelectric thickness is analyzed. The presented threshold voltage model is in a good agreement with the results of TCAD. As a results of our analysis using this analytical threshold voltage model, the change in the threshold voltage with respect to the change in the ferroelectric thickness showed that the threshold voltage increased with the increase of the absolute value of charges in the employed ferroelectric. This suggests that it is possible to obtain an optimum ferroelectric thickness at which the threshold voltage shift becomes 0 V by the voltage across the ferroelectric even when the channel length is reduced. It was also found that the ferroelectric thickness increased as the silicon thickness increased when the channel length was less than 30 nm, but the ferroelectric thickness decreased as the silicon thickness increased when the channel length was 30 nm or more in order to satisfy ΔV_th=0.

• Journal of Power Electronics
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• 제18권5호
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• pp.1336-1346
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• 2018

Wide band gap semiconductor devices such as SiC MOSFETs are becoming the preferred devices for high frequency and high power density converters due to their excellent performances. However, the proportion of the switching loss that accounts for the whole inverter loss is growing along with an increase of the switching frequency. In view of the third quadrant working characteristics of a SiC MOSFET, synchronous rectification discontinuous pulse-width modulation is proposed (SRDPWM) to further reduce system losses. The SRDPWM has been analyzed in detail. Based on a frequency domain mathematical model, a quantitative mathematical analysis of the harmonic characteristic is conducted by double Fourier transform. Meanwhile, a switching loss model and a conduction loss model of inverter for SRDPWM have been built. Simulation and experimental results verify the result of the harmonic analysis of the double Fourier analysis and the accuracy of the loss models. The efficiencies of the SRDPWM and the SVPWM are compared. The result indicates that the SRDPWM has fewer losses and a higher efficiency than the SVPWM under high switching frequency and light load conditions as a result of the reduced number of switching transitions. In addition, the SRDPWM is more suitable for SiC MOSFET converters.

• 전자공학회논문지D
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• 제36D권4호
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• pp.77-85
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• 1999

본 논문은 진성영역에서 공핍증 폭이 선형적으로 변화한다는 가정을 도입하고 전자이동도의 수평 및 수직 전계 이존성을 고려하여 단채널 MOSFET의 {{{{ { I-V }_{ } }}}} 특성에 대한 해석적 모형을 제시하였다. 이 모형으로부터 전 동작영역에 걸쳐 적용되는 문턱전압 방정식과 드레인전류 방정식을 도출하였다. 본 모형의 타당성을 검토하기 위하여 위 식들의 계산을 수행하였고, 그 결과 채널길이가 짧아짐에 따라 문턱전압이 지수함수적으로 감소하였으며, 아울러 채널길이변조, 채널이동로 열화 등을 본 모형에 의하여 일괄적으로 설명할 수 있었다.

• 한국정보통신학회논문지
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• 제16권3호
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• pp.579-584
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• 2012

본 연구에서는 이중게이트(Double Gate; DG) MOSFET에서 발생하는 단채널효과 중 하나인 드레인유기장벽 감소(Drain Induced Barrier Lowering; DIBL)에 대하여 분석하고자 한다. 드레인유도장벽감소 현상은 채널의 길이가 짧아질 때 드레인 전압이 소스측 전위장벽에 영향을 미쳐 장벽의 높이를 감소시키는 현상으로써 단채널에서 발생하는 매우 중요한 효과이다. 본 연구에서는 DIBL을 해석하기 위하여 이미 발표된 논문에서 타당성이 입증된 포아송 방정식의 해석학적 전위분포를 이용할 것이다. 이 모델은 특히 전하분포함수에 대하여 가우시안 함수를 사용함으로써 보다 실험값에 가깝게 해석하였으며 소자 파라미터인 채널두께, 산화막두께, 도핑농도 등에 대하여 드레인유도장벽감소의 변화를 관찰하고자 한다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2001년도 추계종합학술대회
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• pp.665-668
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• 2001

최근 소자의 크기가 작아짐에 따라 집적도가 향상되었으며 크기 감소로 인한 전류-전압 특성의 열화 및 기생 커패시턴스에 의한 성능감쇠가 발생하였다. 이런 문제들을 해결하기 위해 여러 가지 구조들이 개발되고 있으며 본 논문에서는 고농도로 도핑된 ground plane 층위에 적층하여 만든 EPI 구조에 대해 조사 분석하였다. 이 구조의 특성과 임팩트 이온화 및 전계 그리고 I-V 특성 곡선을 저농도로 도핑된 LDD(Lightly Doped Drain) 구조와 비교 분석하였다. 소자의 채널 길이는 0.l0$\mu\textrm{m}$부터 0.06$\mu\textrm{m}$까지 0.01$\mu\textrm{m}$씩 스케일링하여 시뮬레이션 하였다.