• 한국산업정보학회논문지
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• 제22권2호
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• pp.71-78
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• 2017

본 논문에서는 휴대기기용 DC-DC 부스트 컨버터를 설계하였다. 제안하는 DC-DC 부스트 컨버터는 1MHz의 스위칭 주파수로 구동되며, 인덕터, 출력 커패시터, MOS 트랜지스터 등으로 이루어지는 파워단 부분과 보호회로단, 컨트롤블럭단으로 구성하였다. CMOS magnachip $0.18{\mu}m$ 공정을 이용하여 SPICE 모의실험을 통하여 동작을 확인하였고, 칩을 제작하여 모의실험결과와 비교 분석하였다. 설계된 컨버터는 3.3 V 입력 전압 조건에서 출력전압 4.8 V 가 나타났고, 출력전류 95 mA 로 기존의 25~50 mA보다 큰 출력을 얻었다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.212-214
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• 2005

The charge-pump circuit which is used to generate higher voltage than the available supply voltage has wide applications such as the flash memory of EEPROM Because the demand for high voltage comes from physical mechanism such as the oxide tunneling, the required pumped voltage cannot be scaled as the power supply voltage is scaled. Therefore, an efficient charge-pump circuit that can achieve high voltage from the available low supply voltage is essential. A new Analog Switch p-well CMOS charge pump circuit without the MOS device body effect is processed. By improve the structure of the circuit's transistors to reduce the threshold voltage shift of the devices, the threshold voltage of the device is kept constant. So, the circuit electrical characteristics are higher output voltage within a shorter time than the conventional charge pump. The propose analog switch CMOS charge pump shows compatible performance of the ideal diode or Dickson charge pump.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.525-526
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• 2008

This paper proposes a new high-speed level shifter using a special high voltage device with low threshold voltage. Also, novel low voltage swing method is proposed. The high voltage device is a standard LDMOS(Laterally Diffused MOS) device in a $0.18{\mu}m$ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 1.5ns in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

• 센서학회지
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• 제13권2호
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• pp.90-95
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• 2004

Protein and gene detection have been growing importance in medical diagnostics. Field effect transistor (FET) - type biosensors have many advantages such as miniaturization, standardization, and mass-production. In this work, we have fabricated metal-oxide-semiconductor (MOS) FET that operates as molecular recognitions based electronic sensor. Measurements were taken with the devices under phosphate buffered saline solution. The drain current ($I_{D}$) was decreased after forming self-assembled mono-layers (SAMs) used to capture the protein, which resulted from the negative charges of SAMs, and increased after forming protein by 11.5% at $V_{G}$ = 0 V due to the positive charges of protein.

• 전자공학회논문지SC
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• 제46권2호
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• pp.1-6
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• 2009

금속 산화막 반도체 전계효과 트랜지스터(MOSFET)와 트랜지스터(Transistor)와 접합형으로 구성된 절연 게이트 양극성 트랜지스터(IGBT)의 게이트바이어스 상태에서 감마방사선을 조사하면 전기적특성에서 문턱전압과 전류이득의 감소가 발생한다. 저선량과 고선량에서 문턱전압의 이동은 전류의 증감에 따라 변화한다. 본 논문에서 콜렉터전류는 게이트와 에미터간의 전압으로 구동되는데 게이트 바이어스 전압과 조사량에 따라 실험하고 전기적 특성을 분석한다. 그리고 IGBT를 설계하는데 필요한 모델파라미터를 구하고 연구하는데 있다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 추계학술대회
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• pp.642-645
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• 2012

MANET은 기반구조를 사용하지 않은 구조적 한계로 인하여 정보침해에 매우 취약한 특성을 가지고 있다. 제한적 기능을 갖는 단말기에 많은 자원의 가동을 요구하는 침해 대비 기능을 가동시키기 어려운 단점과 방화벽이나 보안 기능이 탑재된 서버와 같은 기반구조의 지원이 수월치 못한 한계점들이 복합적으로 작용되어 발생되는 문제이다. 본 논문에서는 대규모 MANET에서 정보침해 대응 방안의 하나인 IDS(Intrusion Detection System)가 전송성능에 미치는 영향을 분석하고, MANET의 정보침해 취약점을 전송성능 면에서 살펴본다. 본 연구는 일정 이상의 통신영역과 노드수를 가지는 대규모 MANET을 대상으로 하며, 전송 서비스로는 VoIP 기반 음성 트래픽을 사용하였다. 연구 방법으로는 NS-2를 기반으로 한 컴퓨터 시뮬레이션을 이용하였으며, MOS와 호 연결율의 변화를 연구결과로 제시하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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• pp.41-46
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• 2002

In this work, we studied electrical characteristics and leakage current mechanism of Au/$Ta_2O_5$/Si metal-oxide-semiconductor (MOS) devices. $Ta_2O_5$ thin film (63nm) was deposited by atomic layer deposition (ALD) method at temperature of $235^{\circ}C$. The structures of the $Ta_2O_5$ thin films were examined by X-Ray Diffraction (XRD). From XRD, the structure of $Ta_2O_5$ was single phase and orthorhombic. From capacitance-voltage (C-V) analysis, the dielectric constant was 19.4. The temperature dependence of current-voltage (I-V) characteristics of $Ta_2O_5$ thin film was studied from 300 to 423 K. In ohmic region (<0.5 MVcm${-1}$), the resistivity was $2.4056{\times}10^{14}({\Omega}cm)$ at 348 K. The Schottky emission is dominant in lower temperature range from 300 to 323 K and Poole-Frenkel emission dominant in higher temperature range from 348 to 423 K.

• E2M - 전기 전자와 첨단 소재
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• 제7권1호
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• pp.57-63
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• 1994

Aluminum oxide($Al_2{O_3}$) offers some unique advantages over the conventional silicon dioxide( $SiO_{2}$) gate insulator: greater resistance to ionic motion, better radiation hardness, possibility of obtaining low threshold voltage MOS FETs, and possibility of use as the gate insulator in nonvolatile memory devices. We have undertaken a study of the dielectric breakdown of $Al_2{O_3}$ on Si deposited by GAIVBE technique. In our experiments, we have varied the $Al_2{O_3}$ thickness from 300.angs. to 1400.angs. The resistivity of $Al_2{O_3}$ films varies from 108 ohm-cm for films less than 100.angs. to 10$_{13}$ ohm-cm for flims on the order of 1000.angs. The flat band shift is positive, indicating negative charging of oxide. The magnitude of the flat band shift is less for negative bias than for positive bias. The relative dielectric constant was 8.5-10.5 and the electric breakdown fields were 6-7 MV/cm(+bias) and 11-12 MV/cm (-bias).

• 동력기계공학회지
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• 제4권1호
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• pp.45-50
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• 2000

Circuit breakers have traditionally employed mechanical methods to interrupt excessive currents. According to power semiconductor technology advances in power electronic device, some mechanical breakers are replaced with solid state equivalents. Advantages of the contactors using semiconductor devices include faster fault interrupting, fault current limiting, no arc to contain or extinguish and intelligent power control, and high reliability. This paper describes the design of a static $100{\pm}10%V$ and 0 to 50A DC self-protected contactor with 85A "magnetic tripping" and 100A interruption current at $2.2A/{\mu}s$ short circuit of load condition using a new power device the HARRIS MCT (600V-75A). The self-protection circuit of this system is designed by the classical ZnO varistor for energy absorption and turn-off snubber circuit ("C" or "RCD") of the MCT.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.67.1-67.1
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• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.