• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
• /
• pp.3-6
• /
• 2004

반도체 디자인, 공정 기술 및 패기지 기술의 발달에 따라 전력용 반도체는 소형화, 고성능화, 지능화하고 있다. 고속 구동이 용이한 때문에 MOSFET이나 IGBT등의 MOS-gate형 전력 반도체의 발전이 두드려지며, trench, charge balance, NPT 기술등이 패키지 기술과 더불어 이를 위한 주요 기술이 될것으로 보인다. SiC나 GaN등의 Wide Band Gap 물질들을 사용한 차세대 전력 반도체 연구도 활발히 진행되고 있다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제2권3호
• /
• pp.197-204
• /
• 2002

DRAM, SRAM, and FLASH memory are three major memory devices currently used in most electronic applications. But, they have very distinct attributes, therefore, each memory could be used only for limited applications. MRAM (Magneto-resistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. To be a commercially competitive memory device, scalability is an important factor as well. This paper is testing the actual electrical parameters and the scaling factors to limit MRAM technology in the semiconductor based memory device by an actual integration of MRAM core cell. Electrical tuning of MOS/MTJ, and control of resistance are important factors for data sensing, and control of magnetic switching for data writing.

• 한국표면공학회:학술대회논문집
• /
• 한국표면공학회 2015년도 추계학술대회 논문집
• /
• pp.244-245
• /
• 2015

PEALD TiN 금속 전극을 갖는 MOS device에서 SC1 ($NH_4/H_2O_2/H_2O=1:2:5$), SPM ($H_2SO_4/H_2O_2=10:1$), $H_2O_2$ etch chemical을 이용해 TiN 식각 후 oxide 표면 잔류 Ti에 의한 전기적 특성 분석을 진행 하였다. Etch chemical 중 SPM을 이용한 소자의 전기적 특성이 우수하였는데, 이는 잔류Ti atom의 양이 다른 etch chemical을 사용한 것 대비 낮았기 때문이다. 이로 인하여 낮은 leakage current, less frequency dependence의 특성이 관찰되었다. 또한, 후속 열처리를 통해 더욱 우수한 특성이 관찰 되었다. 이러한 공정기술은 single 전극을 갖는 CMOS 형성 시 사용 될 수 있을 것으로 기대된다.

• 한국세라믹학회지
• /
• 제38권9호
• /
• pp.782-786
• /
• 2001

Cobalt silicide has been employed to Embedded DRAM (Dynamic Random Access Memory) and Logic (EDL) as contact material to improve its speed. We have investigated the influences of Ti and TiN capping layers on cobalt-silicided Complementary Metal-Oxide-Semiconductor (CMOS) device characteristics. TiN capping layer is shown to be superior to Ti capping layer with respect to high thermal stability and the current driving capability of pMOSFETs. Secondary Ion Mass Spectrometry (SIMS) showed that the Ti capping layer could not prevent the out-diffusion of boron dopants. The resulting operating current of MOS devices with Ti capping layer was degraded by more than 10%, compared with those with TiN.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제7권3호
• /
• pp.209-213
• /
• 2007

The MOS gate capacitance model presented here is determined by directly solving the coupled Poisson equations on the poly and silicon sides, and includes the polysilicon (poly) gate depletion effect. Our compact gate capacitance model exhibits an excellent fit with measured data and parameter values extracted from data are physically acceptable. The data are collected from 0.5, 0.35, 0.25 and $0.18{\mu}m$ CMOS technologies.

• 한국전기전자재료학회논문지
• /
• 제17권6호
• /
• pp.586-591
• /
• 2004

We studied the dependence of hot-tarrier-induced degradation characteristics on nitrogen concentration in NO(Nitrided-Oxide) gate of nMOS, under ac and dc stresses. The $\Delta$V$_{t}$ and $\Delta$G$_{m}$ dependence of nitrogen concentration were observed, We observed that device degradation was suppressed significantly when the nitrogen concentration in the gate was increased. Compared to $N_2$O oxynitride, NO oxynitride gate devices show a smaller sensitivity to ac stress frequency. Results suggest that the improved at-hot carrier immunity of the device with NO gate may be due to the significantly suppressed interface state generation and neutral trap generation during stress.ess.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제17권3호
• /
• pp.370-377
• /
• 2017

This paper presents a simple noise margin (NM) model of MOS current mode logic (MCML) gates especially in CMOS processes where a large device mismatch deteriorates logic reliability. Trade-offs between speed and logic reliability are discussed, and a simple yet accurate NM equation to capture process-dependent degradation is proposed. The proposed NM equation is verified for 130-nm, 110-nm, 65-nm, and 40-nm CMOS processes and has errors less than 4% for all cases.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 1997년도 춘계학술대회 논문집
• /
• pp.921-926
• /
• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• 전기의세계
• /
• 제26권6호
• /
• pp.86-92
• /
• 1977

The phenomenon of non-steady-state current flow through the interface traps during the dielectric relaxation of MOS device is presented. Experimental method is also described for determining the energy distribution of interface traps, which is based on isothermal dielectric relaxation current technique. Actually, the energy distribution of interface traps was obtained by measuring the transient current through the traps at Si-SiO$_{2}$ interface only in lower-half of the bandgap. It is shown that the trap energy distributio has peak value 1.72*10$^{13}$ cm$^{-2}$ eV$^{-1}$ near 0.73eV approximately.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1988년도 추계학술대회 논문집
• /
• pp.95-97
• /
• 1988

The instability of MOS devices is mainly caused by the oxide charges, and as the need to develop the gate metal grows researches for various new metal gate have been performed, and in these researches, the difference work function existing between the metal and the semiconductor should be considered. Here int his paper, the device is made by the sputtering and the LPCVD method using pure Al, compound metal. poly-si, as a gate metal, the result of the research was shown that the work function difference from using different gate metals effects on the flatband voltage shift. This means we can infer that the threshold voltage adjustment is possible by using different gate metals and this whole mechanism makes the devices behavior more stable.