• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1052-1061
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• 2003

This paper proposes a novel normalization scheme in the state metric calculation unit for the Block-wise MAP Turbo decoder. The proposed scheme subtracts one of four metrics from the state metrics in a trellis stage and shifts, if necessary, those metrics for normalization. The proposed architecture can reduce power consumption and memory requirement by reducing the number of the state metrics by one in a trellis stage in the Block-wise MAP decoder which requires an intensive state metric calculations. Simulation results show that dynamic power has been reduced by 17.9% and area has been reduced by 6.6% in the Turbo decoder employing the proposed normalization scheme, when compared to the conventional Block-wise MAP Turbo decoders.

• The Magazine of the IEIE
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• v.30 no.3
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• pp.309-309
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• 2003

본 논문은 MAP(Maximum A Posteriori) 복호 알고리즘을 이용한 MAP Decoder의 설계에 관해 다룬다. 채널코딩기법은 채널을 통해서 디지털 정보를 전송할 때 신뢰성을 제공하기 위해서 사용되어진다. 즉 수신 단에서 수신된 정보의 오류를 검사하고 수정하기 위한 목적으로 송신 단에서는 디지털 정보에 부가 정보를 첨가해서 전송하게 된다. 그래서 무선 이동 통신에서 성능이 우수한 채널코딩기법은 우수한 통신 품질을 위해서는 필수적이라고 할 수 있다. 최근에 Shannon의 한계에 매우 근접한 성능으로 많이 알려진 오류정정부호로 터보코드가 발표되었고 많은 연구가 진행되고 있다. 터보코드의 부호기로는 RSC(Recursive Systematic Convolutional) 코드가 사용되며 복호 알고리즘으로는 주로 MAP 복호 알고리즘을 사용한다. 본 논문에서 제안된 MAP 복호기는 하드웨어로 구현하기 위해서 변형된 LOG-MAP 복호 알고리즘을 이용하였고 터보디코더의 반복 복호에 이용할 수 있다.

• The Magazine of the IEIE
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• v.30 no.3
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• pp.95-105
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• 2003

본 논문은 MAP (Maximum A Posteriori)복호 알고리즘을 이용한 MAP Decoder의 설계에 관해 다룬다. 채널코딩기법은 채널을 통해서 디지털 정보를 전송할 때 신뢰성을 제공하기 위해서 사용되어진다. 즉 수신 단에서 수신된 정보의 오류를 검사하고 수정하기 위한 목적으로 송신 단에서는 디지털 정보에 부가 정보를 첨가해서 전송하게 된다. 그래서 무선 이동 통신에서 성능이 우수한 채널코딩기법은 우수한 통신 품질을 위해서는 필수적이라고 할 수 있다. 최근에 Shannon의 한계에 매우 근접한 성능으로 많이 알려진 오류정정부호로 터보코드가 발표되었고 많은 연구가 진행되고 있다. 터보코드의 부호기로는 RSC (Recursive Systematic Convolutional) 코드가 사용되며 복호 알고리즘으로는 주로 MAP 복호 알고리즘을 사용한다. 본 논문에서 제안된 MAP 복호기는 하드웨어로 구현하기 위해서 변형된 LOG-MAP 복호 알고리즘을 이용하였고 터보디코더의 반복 복호에 이용할 수 있다.

• Journal of the Korea Society of Computer and Information
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• v.21 no.9
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• pp.51-55
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• 2016

High-capacity, high quality services should be guaranteed in mobile communication environment. Excellent channel coding and compensation techniques are required so as to improve data reliability on fading channels. In this paper, we propose a method using double pilots, estimates and compensates for the fading of information symbols. The proposed method using Log-MAP Turbo decoder through the iterative decoder, improves BER performance under the environment of the frequency selective fading channel. Compared to the existing methods, the suggested methods show functional improvement of approximately 3dB in case that the number of iteration decoding is 5 and BER is $10^{-4}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.39-49
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• 2011

Turbo code needs long decoding time because of iterative decoding. To communicate with high speed, we have to shorten decoding time and it is possible with parallel process. But memory contention can cause from parallel process, and it reduces performance of decoder. To avoid memory contention, QPP interleaver is proposed in 2006. In this paper, we propose MDF method which is fit to QPP interleaver, and has relatively short decoding time and reduced logic. And introduce the design of MAP decode module using MDF method. Designed decoder is targetted to FPGA of Xilinx, and its throughput is 80Mbps maximum.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.4C
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• pp.303-309
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• 2006

By combining the space-time diversity technique and iterative turbo codes, space-time turbo codes(STTCS) are able to provide powerful error correction capability. However, the multi-path transmission and iterative decoding structure of STTCS make the decoder very complex. In this paper, we propose a low complexity decoder, which can be used to decode STTCS as well as general iterative codes such as turbo codes. The efficient implementation of the backward recursion and the log-likelihood ratio(LLR) update in the proposed algorithm improves the computational efficiency. In addition, if we approximate the calculation of the joint LLR by using the approximate ratio(AR) algorithm, the computational complexity can be reduced even further. A complexity analysis and computer simulations over the Rayleigh fading channel show that the proposed algorithm necessitates less than 40% of the additions required by the conventional Max-Log-MAP algorithm, while providing the same overall performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.73-80
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• 2005

The Turbo decoders based on Log-MAP decoding algorithm inherently requires large amount of memory and intensive complexity of hardware due to iterative decoding, despite of excellent decoding efficiency. To decrease the large amount of memory and reduce hardware complexity, the result of previous research. And this paper design the Turbo decoder applicable to the 3G W-CDMA systems. Through the result of previous research, we decided 5-bits for the received data 6-bits for a priori information, and 7-bits for the quantization state metrics. The error correction term for $MAX^{*}$ operation which is the main function of Log-MAP decoding algorithm is implemented with very small hardware overhead. The proposed Turbo decoder is synthesized in $0.35\mu$m Hynix CMOS technology. The synthesized result for the Turbo decoder shows that it supports a maximum 9Mbps data rate, and a BER of $10^{-6}$ is achieved(Eb/No=1.0dB, 5 iterations, and the interleaver size $\geq$ 2000).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12A
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• pp.1387-1395
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• 2004

Turbo decoder inherently requires large memory and intensive hardware complexity due to iterative decoding, despite of excellent decoding efficiency. To decrease the memory space and reduce hardware complexity, various design issues have to be discussed. In this paper, various design issues on Turbo decoder are investigated and the tradeoffs between the hardware complexity and the performance are analyzed. Through the various simulations on the fixed-length analysis, we decided 5-bits for the received data, 6-bits for a priori information, and 7-bits for the quantization state metric, so the performance gets close to that of infinite precision. The MAX operation which is the main function of Log-MAP decoding algorithm is analyzed and the error correction term for MAX* operation can be efficiently implemented with very small hardware overhead. The size of the sliding window was decided as 32 to reduce the state metric memory space and to achieve an acceptable BER.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.1
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• pp.81-88
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• 2004

Turbo code has been adopted in the 3GPP standard, since its performance is very close to the Shannon limit. However, the turbo decoder requires a lot of computations and the amount of the memory increases as the block size of turbo codes becomes larger. In order to reduce the complexity of the turbo decoder, the Log-MAP, the Max-Log-MAP and the sliding window algorithm have been proposed. In this paper, the performance of turbo codes adopted in the 3GPP standard is analyzed by using the floating point and the fixed point implementation. The efficient decoding method is also proposed. It is shown that the BER performance of the proposed method is close to that of the Log-MAP algorithm.

• ETRI Journal
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• v.30 no.1
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• pp.113-128
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• 2008

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.