• Journal of information and communication convergence engineering
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• v.20 no.2
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• pp.137-142
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• 2022

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.614-615
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• 2016

I studied electrical coupling of monolithic 3D inverter(M3D-INV) consisting of Junctionless FET(JLFET). If the thickness of Inter Layer Dielectric (ILD) between top JLFET and bottom JLFET is less than 50nm, current-voltage characteristic of top JLFET is rapidly changed by the gate voltage of bottom JLFET. Therefore, you have to consider about the electrical interaction according to the thickness between top JLFET and bottom JLFET in M3D-INV.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.118-120
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• 2022

This paper investigated the change of threshold voltage according to the influence of work-function variation (WFV) of metal gate in the device structure of monolithic 3-dimension inverter (M3DINV). In addition, in order to investigate the change in threshold voltage according to the electrical coupling of the NMOS stacked on the PMOS, the gate voltages of PMOS were applied as 0 and 1 V and then the electrical coupling was investigated. The average change in threshold voltage was measured to be 0.1684 V, and they standard deviation was 0.00079 V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.529-530
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• 2017

Electrical coupling of monolithic 3D inverter(M3D-INV) consisting of Junctionless FET(JLFET) was investigated. Depending on the thickness of Inter Layer Dielectirc (ILD) between top and bottom JLFETs, $N_{gate}-N_{gate}$ capacitance and transconductance $g_m$ are changed by the gate voltage of bottom JLFET. Therefore, when using a stacked structure with the ILD below tens nm, AC electrical coupling between two transistors in M3D-INV should be considered.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.481-482
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• 2022

In this paper, effect of random dopant fluctuation (RDF) of the top-transistor in a monolithic 3D inverter composed of MOSFET transistors is investigated with 3D TCAD simulation when the gate voltage of the bottom-transistor is changed. The sampling for investigating RDF effect was conducted through the kinetic monte carlo method, and the RDF effect on the threshold voltage variation in the top-transistor was investigated, and the electrical coupling between top-transistors and bottom-transistors was investigated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.5
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• pp.682-687
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• 2022

In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.40-48
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• 2013

This paper presents multi-channel transimpedance amplifier(TIA) arrays in short-range LADAR systems for unmanned vehicles, by using a 0.18um CMOS technology. Two $4{\times}4$ channel TIA arrays including a voltage-mode INV-TIA and a current-mode CG-TIA are introduced. First, the INV-TIA consists of a inverter stage with a feedback resistor and a CML output buffer with virtual ground so as to achieve low noise, low power, easy current control for gain and impedance. Second, the CG-TIA utilizes a bias from on-chip bandgap reference and exploits a source-follower for high-frequency peaking, yielding 1.26 times smaller chip area per channel than INV-TIA. Post-layout simulations demonstrate that the INV-TIA achieves 57.5-dB${\Omega}$ transimpedance gain, 340-MHz bandwidth, 3.7-pA/sqrt(Hz) average noise current spectral density, and 2.84mW power dissipation, whereas the CG-TIA obtains 54.5-dB${\Omega}$ transimpedance gain, 360-MHz bandwidth, 9.17-pA/sqrt(Hz) average noise current spectral density, and 4.24mW power dissipation. Yet, the pulse simulations reveal that the CG-TIA array shows better output pulses in the range of 200-500-Mb/s operations.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.216-218
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• 2008

This paper presents a space vector pulse width modulation (SVPWM) technique for four-switch three-phase (4S3P) inverter topology. The method aims to apply Field Oriented Control (FOC) of Induction motor using 4S3P. The simulations are carried out and the experimental results are given to verify the feasibility of this method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.12
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• pp.1730-1736
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• 2015

This paper presents a 16-channel transimpedance amplifier (TIA) array implemented in a standard $0.18-{\mu}m$ CMOS technology for the applications of panoramic scan LADAR (PSL) systems. Since this array is the front-end circuits of the PSL systems to recover three dimensional image for unmanned vehicles, low-noise and high-gain characteristics are necessary. Thus, we propose a voltage-mode inverter TIA (I-TIA) array in this paper, of which measured results demonstrate that each channel of the array achieves $82-dB{\Omega}$ transimpedance gain, 565-MHz bandwidth for 0.5-pF photodiode capacitance, 6.7-pA/sqrt(Hz) noise current spectral density, and 33.8-mW power dissipation from a single 1.8-V supply. The measured eye-diagrams of the array confirm wide and clear eye-openings up to 1.3-Gb/s operations. Also, the optical pulse measurements estimate that the proposed 16-channel TIA array chip can detect signals within 20 meters away from the laser source. The whole chip occupies the area of $5.0{\times}1.1mm^2$ including I/O pads. For comparison, a current-mode 16-channel TIA array is also realized in the same $0.18-{\mu}m$ CMOS technology, which exploits regulated-cascode (RGC) input configuration. Measurements reveal that the I-TIA array achieves superior performance in optical pulse measurements.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.267-272
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• 2010

In this paper, a Gm-C LPF utilizing common-mode feedforward (CMFF) CMOS inverter type operational transconductance amplifier (OTA) has been designed and verified by circuit simulations. The CMFF CMOS inverter OTA was optimized for wide input linearity and low current consumption using a standard 0.18 ${\mu}m$ CMOS process; gm of 100 ${\mu}S$ and current of 100 ${\mu}A$ at supplied voltage of 1.3 V. Using this optimized CMFF CMOS inverter type OTA, an elliptic 5th order Gm-C LPF for GPS specifications was designed. Gain and frequency tuning of the LPF was done by changing the internal supply voltages. The designed Gm-C LPF gave pass-band ripple of 1.6 dB, stop-band attenuation of 60.8 dB, current consumption of 0.60 mA at supply voltage of 1.2 V. The gain and frequency characteristics of designed Gm-C LPF was unchanged even though the input common-mode voltage is varied.