• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.7
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• pp.1186-1193
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• 2000

In this paper, the system performance with the selection diversity, which is applied to the FH/MFSK system in Nakagami fading channel, is analyzed. The deletion probability is derived from the received signal to noise ratio(SNR) after selection combining and the parameters such as the number of users(M), SNR, Nakagami fading figure(m), and the number of diversity branches(D) is used for the performance analysis of the FH/MFSK system. Assuming that m set 1, it is observed that the bit error rate(BER) is 1.0$\times$$10^{-3}$ and 1.0$\times$$10^{-4}$ at D =1(no diversity) and D=2, respectively, and then is decreased by 10 times. Assuming that m set 2, it is also shown that the BER has a constant value although D is increased. In the case of D=2, the system capacity is more 75% and 20% than that considering no diversity at SNR=15 dB and 25 dB, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.2
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• pp.566-579
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• 2012

Ubiquitous computing called pervasive one is based on the thought of pervading ability of computation in daily life applications. In other words, it aims to include computation in devices such as electronic equipment and automobiles. This has led to disengagement of computers from desktop form. Accordingly, the notice in ubiquitous computing being taken of a world steeped in remote and wireless computer-based-services. Handheld and wearable programmed devices such as sense and control appliances are such devices. This advancement is rapidly moving domestic tasks and life from device-and-human communication to the device-and-device model. This model called Machine to Machine (M2M) has led to acceleration of developments in sciences such as nano-science, bio-science, and information science. As a result, M2M led to appearance of applications in various fields such as, environment monitoring, agricultural, health care, logistics, and business. Since it is envisaged that M2M communications will play a big role in the future in all wireless applications and will be emerged as a progressive linkage for next-generation communications, this paper aims to consider how much M2M architectures can realize ubiquitous computing in daily life applications. This is carried out after acquainting and initiating readers with M2M architectures and arguments for M2M. Some of the applications was not achievable before but are becoming viable owing to emergence of M2M communications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.1-9
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• 2011

Memristor is a portmanteau of "memory resistor". The resistance of memristor is changed depends on the history of electric charge that passed through the device and it is able to memorize the last resistance after turning off the power supply. This paper presents this device that has a high chance to be the next generation of commercial non-volatile memory and its behavior modeling using SPICE simulation. The memristor MOS content addressable memory (M_CAM) is also designed and simulated using the proposed behavioral model. The proposed M_CAM unit cell area and power consumption show an improvement around 40% and 96%, respectively, compare to the conventional SRAM based CAMs. The M_CAM layout is also implemented using 0.13${\mu}m$ mixed-signal CMOS process under 1.2 V supply voltage.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.28 no.9
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• pp.40-43
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• 2010

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.59-67
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• 2007

This paper presents a low power dual-level low voltage differential signaling (DLVDS) technique using current source switching for LCD driver ICs in portable products. The transmitter makes dual level signal that has two different level signal 400mVpp and 250mVpp while keeping the advantages of LVDS. The decoding circuit recovers the primary signal from DLVDS. The low power DLVDS is implemented using a $0.25{\mu}m$ CMOS process under 2.5V supply. The proposed circuit shows 800Mbps/2-line data rate and 9mW, 11.5mW power consumptions in transmitter and receiver, respectively. The proposed DLVDS scheme reduce power consumption dramatically compare with conventional one.

• The Transactions of the Korea Information Processing Society
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• v.1 no.1
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• pp.105-113
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• 1994

This paper introduces the Parallel Advanced Loosely coupled Multiprocessor (PALM) architecture, which is based on HCH(m,p), where m is number of links per a communication processor (CP) and p is the number of application processors (APs) connected to the CP. communication links between a pair of CPs and/or between a CP and an AP, are made of dual-Port RAMs, which provide fast and reliable word-parallel communication between processors. Among the wide spectrum of HCH networks, HCH(m,2) is also known to be a cost optimal topology, such that HCH(m,2) consists of the largest number of APs retaining the minimal number of CPs and communication links. We also implement a testbed based on HCH(2,2). The experiment result shows that the small communication/computation ratio of the PALM system would realize fine-grain parallelism on message-passing MIMD systems.

• Korean Journal of Optics and Photonics
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• v.15 no.2
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• pp.158-170
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• 2004

Wireless optical communication is expected for high-speed optical communication in the areas of saturated optical fiber communication and low population density. In this paper, we present an optical transmitter system for wireless optical communication with new design concepts different from the usual optical imaging system. The specifications are the following: the source is a laser diode(LD) of wavelength 830 nm in which the divergent angle from the tangential plane differs from that from the sagittal plane. Here, the requested transmission distances are very long range such as 500 m to 1500 m and beam diameter is 3 m at the receiver with symmetrical energy distribution. For the evaluation characteristics of this kind of non-imaging system, two optical quantities, the relative illumination distribution and energy transfer efficiency, are numerically calculated through lots of ray tracing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2216-2222
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• 2014

A recent trend of increasing container traffic volume using reefer container demands continuous management of reefer container in transit. However, reefer containers can only be monitored at terminal or in ship during marine transportation instead of throughout entire section. In the case of inland transportation section using truck or train, monitoring is not possible currently. The reason is because the reefer container monitoring method using PCT recommended by IMO and conventional monitoring methods using TCP/IP, RFID communication require establishing additional communication infrastructure. This paper will propose a new reefer container control device that not only solves these problems and monitors during inland transportation section but also controls reefer container. Using data port attached to every reefer container, the proposed device collects the information of reefer container and using M2M communication technology, it transmits information to server without the need to establish additional communication infrastructure. In addition, it can control the operational status of reefer container upon receiving control information set in server such as temperature of reefer container.