• 제목/요약/키워드: M-power class (N)

검색결과 39건 처리시간 0.021초

Spectral mapping theorem and Weyl's theorem

  • Yang, Young-Oh;Lee, Jin-A
    • 대한수학회논문집
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    • 제11권3호
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    • pp.657-663
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    • 1996
  • In this paper we give some conditions under which the Weyl spectrum of an operator satisfies the spectral mapping theorem for analytic functions. Also we show that Weyl's theorem holds for p(T) where T is an operator of M-power class (N) and p is a polynomial on a neighborhood of $\sigam(T)$. Finally we answer an old question of Oberai.

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MOSFET의 특성변화에 따른RF 전력증폭기의 신뢰성 특성 분석 (Reliability Characteristics of RF Power Amplifier with MOSFET Degradation)

  • 최진호
    • 한국정보통신학회논문지
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    • 제11권1호
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    • pp.83-88
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    • 2007
  • MOSFET 트랜지스터의 전기적인 특성 변화에 따른 Class-E RF 전력 증폭기의 신뢰성 특성을 분석하였다. Class-E 전력 증폭기에서 MOSFET는 높은 효율을 얻기 위해 스위치로 동작하며, 이로 인해 MOSFET가 off 되었을 때 드레인 단자에 높은 전압 신호가 발생한다. 회로가 동작함에 따라 높은 전압의 스트레스로 인하여 MOSFET의 문턱 전압은 증가하고 전자의 이동도는 감소하여 MOSFET의 드레인 전류는 감소하게 된다. Class-E 전력 증폭기에서 MOSFET의 전류가 감소하면 전력 효율 및 출력 전력은 감소하게 된다. 그러나 class-E 전력증폭기에서 작은 부하 인덕터를 사용할 경우 큰 인덕터를 사용하는 경우에 비 해 신뢰성 특성을 향상시킬 수 있다. 1mH의 부하 인덕터를 사용한 경우 $10^{7}$초 후에 드레인 전류는 46.3%가 감소하였으며, 전력 효율은 58%에서 36%로 감소하였다. 그러나 1nH의 부하 인덕터를 사용한 경우 드레인 전류는 8.89%, 전력 효율 59%에서 55%로 감소하여 우수한 신뢰성 특성을 보여주었다.

Evaluation of GaN Transistors Having Two Different Gate-Lengths for Class-S PA Design

  • Park, Jun-Chul;Yoo, Chan-Sei;Kim, Dongsu;Lee, Woo-Sung;Yook, Jong-Gwan
    • Journal of electromagnetic engineering and science
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    • 제14권3호
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    • pp.284-292
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    • 2014
  • This paper presents a characteristic evaluation of commercial gallium nitride (GaN) transistors having two different gate-lengths of $0.4-{\mu}m$ and $0.25-{\mu}m$ in the design of a class-S power amplifier (PA). Class-S PA is operated by a random pulse-width input signal from band-pass delta-sigma modulation and has to deal with harmonics that consider quantization noise. Although a transistor having a short gate-length has an advantage of efficient operation at higher frequency for harmonics of the pulse signal, several problems can arise, such as the cost and export license of a $0.25-{\mu}m$ transistor. The possibility of using a $0.4-{\mu}m$ transistor on a class-S PA at 955 MHz is evaluated by comparing the frequency characteristics of GaN transistors having two different gate-lengths and extracting the intrinsic parameters as a shape of the simplified switch-based model. In addition, the effectiveness of the switch model is evaluated by currentmode class-D (CMCD) simulation. Finally, device characteristics are compared in terms of current-mode class-S PA. The analyses of the CMCD PA reveal that although the efficiency of $0.4-{\mu}m$ transistor decreases more as the operating frequency increases from 955 MHz to 3,500 MHz due to the efficiency limitation at the higher frequency region, it shows similar power and efficiency of 41.6 dBm and 49%, respectively, at 955 MHz when compared to the $0.25-{\mu}m$ transistor.

ON NONNIL-m-FORMALLY NOETHERIAN RINGS

  • Abdelamir Dabbabi;Ahmed Maatallah
    • 대한수학회논문집
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    • 제39권3호
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    • pp.611-622
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    • 2024
  • The purpose of this paper is to introduce a new class of rings containing the class of m-formally Noetherian rings and contained in the class of nonnil-SFT rings introduced and investigated by Benhissi and Dabbabi in 2023 [4]. Let A be a commutative ring with a unit. The ring A is said to be nonnil-m-formally Noetherian, where m ≥ 1 is an integer, if for each increasing sequence of nonnil ideals (In)n≥0 of A the (increasing) sequence (∑i1+⋯+im=nIi1Ii2⋯Iim)n≥0 is stationnary. We investigate the nonnil-m-formally Noetherian variant of some well known theorems on Noetherian and m-formally Noetherian rings. Also we study the transfer of this property to the trivial extension and the amalgamation algebra along an ideal. Among other results, it is shown that A is a nonnil-m-formally Noetherian ring if and only if the m-power of each nonnil radical ideal is finitely generated. Also, we prove that a flat overring of a nonnil-m-formally Noetherian ring is a nonnil-m-formally Noetherian. In addition, several characterizations are given. We establish some other results concerning m-formally Noetherian rings.

Power Comparison of Independence Test for the Farlie-Gumbel-Morgenstern Family

  • Amini, M.;Jabbari, H.;Mohtashami Borzadaran, G.R.;Azadbakhsh, M.
    • Communications for Statistical Applications and Methods
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    • 제17권4호
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    • pp.493-505
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    • 2010
  • Developing a test for independence of random variables X and Y against the alternative has an important role in statistical inference. Kochar and Gupta (1987) proposed a class of tests in view of Block and Basu (1974) model and compared the powers for sample sizes n = 8, 12. In this paper, we evaluate Kochar and Gupta (1987) class of tests for testing independence against quadrant dependence in absolutely continuous bivariate Farlie-Gambel-Morgenstern distribution, via a simulation study for sample sizes n = 6, 8, 10, 12, 16 and 20. Furthermore, we compare the power of the tests with that proposed by G$\ddot{u}$uven and Kotz (2008) based on the asymptotic distribution of the test statistics.

0.35um BCD공정을 사용한 Class-D Amplifier (Class-D Amplifier using 0.35um BCD process)

  • 한상진;황승현;박시홍
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2007년도 하계학술대회 논문집
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    • pp.271-273
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    • 2007
  • 본 논문에서는 TV나 Audio등에 사용되는 2채널 30W급 Class-D amplifier를 동부하이텍의 0.35um BD350BA 공정을 사용하여 디지털 방식의 Class-D amplifier 출력단 구동에 적합하도록 설계하였다. 출력단은 Bootstrap 전원을 사용한 N-N type의 30V LDMOS 내장형이며 각각 $250m{\Omega}$의 턴 온 저항을 갖게 설계 되었다. THD+N 특성개선을 위한 Dead time 및 Delay 조정회로를 내장하였으며 보호회로로는 Over current, Over temperature, UVLO 가 있다.

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AB급 CMOS 전류 콘베이어(CCII)에 관한 연구 (A study of class AB CMOS current conveyors)

  • 차형우;김종필
    • 전자공학회논문지C
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    • 제34C권10호
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    • pp.19-26
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    • 1997
  • Novel class AB CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well CMOS process for high-frequency current-mode signal processing were developed. The CCII for low power operation consists of a class AB push-pull stage for the current input, a complementary source follower for the voltage input, and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated CCII show that the current input impedance is 875.ohm. and the bandwidth of flat gain when used as a voltage amplifier extends beyond 4MHz. The power dissipation is 1.25mW and the active chip area is 0.2*0.15[mm$\^$2/].

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Fabrication of 6 cm Class YBaCuO Single Crystal

  • Park, B.S.;Han, S.C.;Han, Y.H.;Jeong, N.H.;Yun, H.J.;Kim, K.J.;Oh, J.M.;Sung, T.H.
    • 한국초전도학회:학술대회논문집
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    • 한국초전도학회 2003년도 High Temperature Superconductivity Vol.XIII
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    • pp.33-33
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    • 2003
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LCD 드라이버에 적용 가능한 저소비전력 및 높은 슬루율을 갖는 이중 레일 투 레일 버퍼 증폭기 (A Low-Power High Slew-Rate Rail to Rail Dual Buffer Amplifier for LCD output Driver)

  • 이민우;강병준;김한슬;한정우;손상희;정원섭
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2013년도 추계학술대회
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    • pp.726-729
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    • 2013
  • 본 논문에서는 LCD source driver IC의 output buffer op-amp로 사용가능한 저소비전력 및 높은 슬루율을 갖는 CMOS rail-to rail 입/출력 op-amp를 설계하였다. 제안한 op-amp는 기존의 출력단 Class-AB 단에 새로이 설계한 Class-B control단을 추가하여 저소비전력과 높은 슬루율을 갖게 하였다. 시뮬레이션 결과 제안된 op-amp는 소비전력이 1.19mW로 감소하였으며 사용한 부하커패시터 (10nF)를 기준으로 슬루율은 6.5V/us로 확인되었다.

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60 N.m급 플렉서블 디스크 커플링 구조해석 및 최적화 (A Structural Analysis and Optimization of a 60 N.m Class Flexible Disk Coupling)

  • 이현규;김병로;김성묵;김종봉
    • 한국생산제조학회지
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    • 제22권5호
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    • pp.774-781
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    • 2013
  • A structural analysis was carried out for a 60 N.m class flexible disk coupling. Flexible disk couplings are used to transmit power between two shafts. When a flexible coupling is used, some amount of misalignments such as angle of deviation and end play can be allowed in assembling the shafts. However, the maximum allowable misalignment should be decided to guarantee the fatigue life. In this study, the effect of the angle of deviation and end play on the maximum stress was investigated. From the analysis results, it was shown that the angle of deviation has a greater effect on the maximum stress than the end play. Furthermore, the dimensions of the disk plate were optimized to realize a better design. From the optimization, the maximum stress could be reduced by up to 5.2%.