• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.1394-1397
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• 1993

A Fuzzy Microprocessor(FMP) is presented, which is suitable for real-time control applications. The features include high speed inference of maximum 114K FLIPS at 20MHz system clocks, capability of up to 128-rule construction, and handing of 8 input variables with 8-bit resolution. In order to realize these features, the fuzzifier circuit and the processing element(PE) are well optimized for LSI implementation. The chip fabricated in 1.2$\mu\textrm{m}$ CMOS technology contains 71K transistors in 82.8 $\textrm{mm}^2$ die size and is packaged in 100-pin plastic QFP.

• 재활복지
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• 제21권4호
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• pp.101-118
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• 2017

본 연구는 가상현실 게임이 노인 뇌졸중 환자의 우울, 대인관계, 삶의 만족도에 미치는 효과를 알아보기 위하여 실시되었다. 연구대상은 65세 이상의 뇌졸중 노인 40명으로, 전통적 작업치료만 실시한 대조군과 전통적 작업치료와 2인이 함께 가상현실 게임을 수행한 실험군에 각각 20명씩 무선배치하여 총 12주간 실시하였다. 실험군에게 적용된 가상현실 게임은 Nintendo Wii Sports Resort 프로그램을 적용하였고, 대상자의 심리 사회적요인을 알아보기 위해 우울증 척도 (Beck Depression Inventory; BDI), 대인관계 변화 척도(Relationship change scale; RCS), 삶의 만족도(Life Satisfaction Index-Z; LSI-Z)를 이용하여 실험 전과 실험 후의 평가를 시행하였다. 이에 대한 연구결과는 다음과 같았다. 첫째, 심리 사회적(우울, 대인관계)변화를 살펴본 결과 우울은 두 군 모두, 대인관계는 실험군에서만 통계적으로 유의한 향상을 나타났다(p<.001). 둘째, 삶의 만족도의 변화를 본 결과 대조군(p<.05), 실험군(p<.001) 모두에서 통계적으로 유의한 향상을 보였다. 셋째, 우울, 대인관계 및 삶의 만족도와의 상관관계를 본 결과 우울증, 대인관계는 삶의 만족도와 통계적으로 유의한 상관관계를 보였다(p<.05). 이상의 결과를 정리하면 2인이 함께 수행하는 가상현실 게임이 뇌졸중 노인환자의 심리 사회적요인(우울, 대인관계)과, 삶의 만족도에 유의미한 효과가 있음이 알 수 있었다.

• 한국생산제조학회지
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• 제7권1호
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• pp.58-68
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• 1998

Advantages of adhesively bonded joints and techniques of weight reduction have led to increasing use of structural adhesives such as LSI(large scale integration) package, automobile, aircraft in the various industries. In spite of such wide applications of adhesively bonded joints, the evaluation method of bonding strength has not been established. Stress singularity occurs at the interface edges of adhesively bonded joints and it is required to analyze it. In this paper, the stress singularity using 2-dimensional elastic boundary element method (BEM) with the changes of the lap length and adhesive for single lap joint was analyzed, and experiments of strength evaluation were carried out. As the results, the evaluating method of bonding strength considering stress singularity at interface edges of adhesively bonded joints and stress intensity factor of interface crack have been proposed in static and fatigue test.

• ETRI Journal
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• 제7권4호
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• pp.11-14
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• 1985

바이폴라 소자로 구성된 회로가 양호한 특성을 갖기 위해서는 개별 소자의 동작 속도, 집적도 및 전력 소비 특성이 좋아야 한다. 그런데 지금까지 주로 사용해온 기존의 SBC 바이폴라 트랜지스터로는 이들 특성을 개선하는 데는 한계가 있었다. 일반적으로 바이폴라 트랜지스터는 면적이 줄어듦에 따라 이들 특성이 개선되므로 본 연구에서는 SBC 방법과는 다른 PSA 공정 방법을 개발하였다. 즉, 소자 격리에서의 종래의 PN 접합에 의한 방법과 다른 산화막에 의한 방법을 도입하였고 또한 에미터, 베이스 사이의 거리를 최소로 줄이기 위하여 다결정 실리콘에 의한 polysilicon self-align 방법으로 에미터 및 베이스를 형성시켰다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.137-140
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• 2002

In this paper, a new algorithm for two-dimensional (2-D) finite-difference time-domain (FDTD) method is presented. By this new method, the maximum time step size can be increased over the Courant-Friedrich-Levy (CFL) condition restraint. This new algorithm is adapted from an Alternating-Direction Implicit FDTD (ADI-FDTD) method. However, unlike the ADI-FDTD algorithm. the alternation is performed with respect to the blocks of fields rather than with respect to each respective coordinate direction. Moreover. this method can be efficiently simulated with parallel computation. and it is more efficient than the conventional FDTD method in terms of CPU time. Numerical formulations are shown and simulation results are presented to demonstrate the effectiveness and efficiency of our proposed method.

• 전기전자학회논문지
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• 제3권1호
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• pp.39-49
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• 1999

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.

• 대한전자공학회논문지
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• 제19권5호
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• pp.48-54
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• 1982

반도체 기술은 갖지 않고 설비나 자금에만 의존한다면 IC, LSI의 실습 교육은 물론 연구도 실현될 수 없다. 집원자로의 제작방법, 즉 웨이커 프로세스에 있어서 허락되는 조건이 시스템 구성, 논리 및 전자 회로 설계의 기준이 되므로. 고안된 제작 방법이 전 공정을 통하여 확립되지 않으면 안된다. 학생은 매년 새로이 들어 오고 나가며 유동성이 심하다. 단기간(2∼3주간)의 훈련으로 필요한 기술을 쉽게 터득할 수 있도록 개선된 프로세스의 구체적인 예를 들어 본다. 아울러, 장기의 전망에 의거한 연구를 구체적으로 진전시키는 예도 함께 보였다.

• Journal of information and communication convergence engineering
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• 제3권3호
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• pp.142-145
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• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• 대한전자공학회논문지
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• 제27권12호
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• pp.1841-1851
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• 1990

Self-aligned gate GaAs MESFETs using ion beam deposited tungsten applicable to GaAs LSI fabrication process have been fabricated. Silicon implanted samples were annealed using isothermla two step RTA process and conventional one step RTA process. The electrical and physicla characteristics of annealed samples were investigated using Hall and I-V measurements. As results of measurements, activation characteristics of the isothermal two step RTA process are better than those of one step annealed ones. Using the developed processes, GaAs SAFETs (Self-Aligned Gate FET) have been fabricated and electdrical characteirstics are measured. As results, subthreshold currents of SAGFETs are 6x10**-10 A/\ulcorner, that is compatible to conventional MESFET, maximum transconductances of 0.75\ulcorner gate MESFET using one step RTA process and 2\ulcorner gate MESFET using isothermal two step RTA process are 18 mS/mm, 41 mS/mm respectively.

• The Korean Journal of Ceramics
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• 제1권2호
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• pp.96-100
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• 1995

Recently, alumina/glass composites have been applied as a substrate material for hybrid IC and LSI multi-chip packaging. In this study, the characterization of sodium borosilicate glasses containing NaF and $AlF_3$ and the preparation of the resulted glass/alumina composites have been examined and the effect of the addition of fluorides on the thermal. and dielectric properties of the sintered composites have been studied. The sintering temperature of specimens was lowered by about 100-$150^{\circ}C$ by the addition of fluorine compared with the specimens without fluorine. The specimens containing fluorine showed slightly lower dielectric constants than those of the specimens without fluorine.