• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.4
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• pp.807-811
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• 2001

In this paper we proposed a dual-frequency circular sector microstrip antenna with orthogonal polarized modes and high isolation between the two feeding ports. And then we designed a transceiver operating at 5.6 GHz for transmitting and at 5.5 GHz for receiving. The good isolation provided by the proposed antenna is used as the basis for the transmit-receive filtering of transceiver. The operating frequencies and polarization characteristics of the proposed antenna is calculated by using a cavity model. The 5-parameters and radiation patterns of the antenna are measured. A power amplifier and a low noise amplifier are designed and integrated with antenna to make a transceiver, which has about 13dB transmitting gain and about 8㏈ receiving gain.

• ETRI Journal
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• v.43 no.2
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• pp.197-208
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• 2021

Single-carrier frequency division multiple access (SC-FDMA) is currently being used in long-term evolution uplink communications owing to its low peak-to-average power ratio (PAPR). This study proposes a new transceiver design for an SC-FDMA system based on Walsh-Hadamard transform (WHT). The proposed WHT-based SC-FDMA system has low-PAPR and better bit-error rate (BER) performance compared with the conventional SC-FDMA system. The WHT-based SC-FDMA transmitter has the same complexity as that of discrete Fourier transform (DFT)-based transmitter, while the receiver's complexity is higher than that of the DFT-based receiver. The exponential companding technique is used to reduce its PAPR without degrading its BER. Moreover, the performances of different ordered WHT systems have been studied in additive white Gaussian noise and multipath fading environments. The proposed system has been verified experimentally by considering a real-time channel with the help of wireless open-access research platform hardware. The supremacy of the proposed transceiver is demonstrated based on simulated and experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.2B
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• pp.130-137
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• 2012

In this paper, we propose core and edge router architectures with LPI(Low Power Idle) for reducing energy consumption in OBS networks. The proposed core router architecture is comprised of a BCP switch, a burst switch, line cards and sleep/wake controller for LPI. When the offered load of network is low, sleep/wake controller can change the state of the core router line card from active to sleep state for saving the energy after receiving network control packet. The edge router consists of a switch for access line card, a SCU and OBS edge router line cards. The LPI function in edge router line card is performed through network level control by network control packet, individually. Additionally, PHY/transceiver modules can transition active state to sleep state when burst assemble engine generates new bursts. To evaluate the energy saving performance of proposed architecture with LPI, the power consumption of each router is analyzed by using data sheet of commercial router and optical device. And, simulation is also performed in terms of sleep time of PHY/Transceiver through OPNET.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12B
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• pp.1677-1685
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• 2001

In this paper, we propose a call admission control scheme that can be performed within guaranteeing of required QoS(Quality of Services) in DS-CDMA(Direct Sequence-Code Division Multiple Access) reverse link. It has been performed rely on a physical channel numberonly and based on quality of received signal from MODEM(modulator/demodulator) part in established study. In other methods, the standard for services would have been set from statistical analysis of users\` location and using received power level in BTS(Base Transceiver Station). These ways bring about not only system loads but time delay or great differences from real environment. To solve these problems, we propose a call drop rate estimation algorithm for the purpose of call admission control based on measured value at LNA(Low Noise Amplifier) ports of BTS(Base Transceiver Station) in real time. This method proposed in this paper estimates a quality of offered service in real time, reduce system loads and shorten time delay which is needed to determine the standard for call admission control. But it requires a additional 17W complexity which can measure received signal power in BTS and estimate call drop rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.7-13
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• 2009

This paper presents a multi-channel transceiver that achieves a data rate of 3.125Gb/s/ch. The LVDS is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. On the receiver side, a low-power CDR(clock and data recovery) using 1/4-rate clock based on dual-interpolator is proposed. The CDR generates needed additional clocks in each recovery part internally using only inverters. Therefore each part can be supplied with the same number of 1/4-rate clocks from a clock generator as in 1/2-rate clock method. Thus, the reduction of a clock frequency relaxes the speed limitation and lowers power dissipation. The prototype chip is comprised of two channels and was fabricated in a $0.18{\mu}m$ standard CMOS process. The output jitter of transmitter is loops, peak-to-peak(0.31UI) and the measured recovered clock jitter is 47.33ps, peak-to-peak which is equivalent to 3.7% of a clock period. The area of the chip is $3.5mm^2$ and the power consumption is about 119mW/ch.

• ETRI Journal
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• v.26 no.3
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.11
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• pp.1304-1310
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• 2010

This study is to design FMCW radar transceiver of K-band which is used to detect and track approaching high speed targets with low altitude. The transmitter needs high output power due to small RCS targets and wide beamwidth of transmit antenna. Multi-channel receivers are required to detect and track targets by interferometer method. Transmitter consists of high power amplifier, waveguide switch, and frequency up-converter. Receiver is composed of five channel receivers, up and down converters, X-band local oscillator and waveform generator. Before manufacturing it, the proposed architecture of transceiver is proved by modeling and simulation using several parameters. Then, it is manufactured by using industrial RF components. The performance parameters are measured through experiment. In the experiment, transmitting power and receiver gain were measured with 39.64 dBm and 29.1 dB, respectively. All other parameters in the specification were satisfied as well.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.9
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• pp.4107-4111
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• 2011

Therapeutic rehabilitation moped wired to process the data, because it is a complicated installation and configuration in terms of space utilization for people with disabilities have many difficulties. In this study, considering the economic costs and health-related engineering technology to develop its roots and rehabilitation of electric bicycles for the RF transceiver board data processing were developed. In particular, the low power RF transceiver in the ISM frequency bands of radio stations using the number of modules, electric bicycles and one was to enable the processing of data between PC.

• Journal of Communications and Networks
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• v.18 no.5
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• pp.762-772
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• 2016

This paper studies the problem of precoding and post-coding design for multicell multiuser downlink transmissions in the absence of perfect channel state information (CSI). Using statistical information of imperfect CSI, an iterative multiuser multicell transceiver design is formulated by minimizing the mean squared error (MSE) cost function of signal and leakage interference under per-base station power constraint (PBPC). The convergence of the iterative precoding and postcoding algorithm is verified by analytical and empirical results. The proposed precoding and postcoding algorithm offers a low computational complexity and robustness against CSI imperfection.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.129-132
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• 2000

In this paper, a 1.8㎓ low noise amplifier was designed and simulated using 0.2$\mu\textrm{m}$ Si CMOS process. Noise characteristics and s parameters were extracted for the 300$\mu\textrm{m}$ gate width and 0.25$\mu\textrm{m}$ gate length NMOS transistors. For high available power gain, each stage was designed cascode type. It revealed available power gain of 23.5dB, noise figure of 2.0dB, power consumption of 15㎽ at 2.5V. It was shown that designed low noise amplifier had good RF performance. Designed Si CMOS LNA is expected to be used for RF front-end in transceiver.