• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2011.06a
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• pp.329-330
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• 2011

This paper concerns to the acquisition of Global Positioning System L1 C/A coded signals. It specifically addresses the issues of acquiring very low power signals which are attenuated due to special circumstances such as indoor environment or forest canopy etc. The proposed post-processing algorithm applies modified signal folding coherent integration scheme on weak signal record. It dynamically compensates the doppler effect on the length of C/A code before integrating the signal power. Experimental results show effectiveness of the algorithm on weak GPS signals recorded in a real environment.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.39-45
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• 2009

OFDM is used for achieving a high-speed data transmission in mobile wireless communication systems. Conventionally, fast Fourier transform that is the main signal processing of OFDM is implemented using digital signal processing. The DSP FFT LSI requires large power consumption. Current-mode FFT LSI with analog signal processing is one of the best solutions for high speed and low power consumption. However, for the operation of current-mode FFT LSI that has the structure of parallel-input and parallel-output, current-mode serial-to-parallel and parallel-to-serial converter are indispensable. We propose a novel current-mode SPC and PSC and full chip simulation results agree with experimental data. The proposed current-mode SPC and PSC promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.64-69
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• 2014

Ultrasound system is one of the complex wireless signal processing systems that are widely used in the fields of modern industry such as medical diagnostics, underwater communications, and sensor-networks. Miniaturization of ultrasound system has been raging recently. In this paper, a hybrid LNA that is suitable for miniaturization and mobile diagnostic ultrasound system has been developed. The proposed LNA has low noise figure of less than 5dB, and the feedback resistor is designed to be electrically adjusted in order to attain the impedance-matching for various ultrasound transducers. It supports the whole ultrasound frequencies from 10KHz to 150MHz frequency band and also provides sleep modes. A gain from -18.8 to -29.5 dB is achieved by adjusting each transducer to fit the system character. Power consumption can be reduced up to 90% in similar performance as compared to the existing LNA.

• Transactions on Electrical and Electronic Materials
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• v.16 no.1
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• pp.16-19
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• 2015

A wearable sensing ECG T-shirt for ubiquitous vital signs sensing is proposed. The sensor system consists of a signal processing board and capacitive sensing electrodes which together enable measurement of an electrocardiogram (ECG) on the human chest with minimal discomfort. The capacitive sensing method was employed to prevent direct ECG measurement on the skin and also to provide maximum convenience to the user. Also, low power integrated circuits (ICs) and passive electrodes were employed in this research to reduce the power consumption of the entire system. Small flexible electrodes were placed into cotton pockets and affixed to the interior of a worn tight NIKE Pro combat T-shirt. Appropriate signal conditioning and processing were implemented to remove motion artifacts. The entire system was portable and consumed low power compared to conventional ECG devices. The ECG signal obtained from a 24 yr. old male was comparable to that of an ECG simulator.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1698-1699
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• 2007

This paper deals with the surge measurement system for low voltage power line of industrial plants. It consists of a capacitive divider, A/D conversion part, signal processing and control part. A FPGA and a DSP board were designed to fast signal processing and control. Also, in order to measure lightning surge and switching surge for a long time, data backup device was applied by using SD memory. A performance of the measurement system was verified through evaluation test using impulse calibration generator.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1019-1022
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• 2003

This paper has proposed a 4- bit 20MHz Flash A/D converter design available analog signal processing and realized its intergrated circuit. The parallel comparison method A/D converter quantized analog signals swiftly using various converters. Also this theme has designed economic power dissipation circuit using a preamplifier of low volt & power CMOS comparator. Also the system was fabricated by Hynix 0.35um CMOS process.

• ETRI Journal
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• v.30 no.3
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• pp.451-460
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• 2008

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low-power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and parallel-pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel-pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.144-155
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• 2013

This paper presents a low-cost remote power-quality-failure monitoring system (RPMS) using Android App and TI MCU (micro-controller unit), which is appliable to a micro-grid. The designed RPMS testbed consists of smart nodes, a server, and Android APPs. Especially, the C2000-series MCU-based RPMS smart node that is low-cost compared to existing monitoring systems has both a signal processing function for power signal processing and a data transmission function for power-quality monitoring data transmission. The signal processing function implements both a wavelet-based power failure detection algorithm including sag, swell, and interruption, and a FFT-based power failure detection algorithm including harmonics such that reliable and real-time power quality monitoring is guaranteed. The data transmission function implements a low-complexity RPMS transmission protocol and defines a simple data format (msg_Diag) for power monitoring message transmission. We may watch the monitoring data in real time both at a server and Android phone Apps connected to the WiFi network (or WAN). We use RS-232 (or Bluetooth) as the wired (or wireless) communication media between a server and nodes. We program the RPMS power-quality-failure monitoring algorithm using C language in the CCS (Code Composer Studio) 3.3 environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1259-1264
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• 1999

In this paper, the High-speed, Low-power Analog-Digital Conversion Archecture is porposed using the Pipelined archecture for High-speed conversion rate and the Successive-Approximation archecture for Low-power consumption. This archecture is the Successive-Approximation archecture using Pipelined Comparator array to change reference voltage during Holding Time. The Analog-to-Digital Converter for video processing is designed using 0.8${\mu}{\textrm}{m}$ CMOS tchnology. When an 6-bit 10MS/s Analog-to-Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 37dB at a sampling rate of 10MHz with 100KHz sine input signal. The power consumption is 1.46mW at 10MS/s. When an 8-bit 10MS/s Analog-to Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41dB at a sampling rate of 100MHz with 100KHz sine input signal. The power consumption is 4.14m W at 10MS/s.