• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1993-1999
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• 2011

This paper describes a design of area-efficient/low-power cryptographic processor for HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a 0.35-${\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.895-898
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• 2005

This paper describes a design of LNS-based divider and square-root circuits which are key arithmetic units in graphic processor and digital signal processor. To achive area-efficient and low-power that is an essential consideration for mobile environment, a fixed-point format of 16.16 is adopted instead of conventional floating-point format. The designed divider and square-root units consist of binary-to-logarithm converter, subtractor, logarithm-to-binary converter. The binary to logarithm converter is designed using combinational logic based on six regions approximation method. As a result, gate count reduction is obtained when compared with conventional lookup approack. The designed units is 3,130 gate count and 1,280 gate count. To minimize average percent error 3.8% and 4.2%. error compensation method is employed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.4
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• pp.574-579
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• 2012

In this paper, the battery charger developed which is satisfy by the characteristics of the rapid control and reduce the cost of the charger. analog-digital mixed mode controller developed with dedicated IC for PWM control and low-performance micro-processor is using for the operation control of charger. The low-cost NEV charger developed to verify the performance and usability is verified with charging battery experiment by of using developed charger.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.78-86
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• 2010

This paper discusses the programming model of SODA-II that is a baseband processor for software defined radio (SDR) systems. Signal processing On-Demand Architecture Ⅱ (SODA-II) is an on-chip multiprocessor architecture consisting of four processor cores and each core has both an wide SIMD datapath and a scalar datapath. This architecture is appropriate for baseband processing that is a mixture of vector computations and scalar computations. The programming model of the SODA-II is based on C library routines. Because the library routines hide the details of complex SIMD datapath control procedures, end users can easily program the SODA-II without deep understanding on its architecture. In this paper, we discuss the details of library routines and how these routines are exploited in the implementation of baseband signal processing algorithms. As application examples, we show the implementation result of W-CDMA multipath searcher and OFDM demodulator on the SODA-II.

• Journal of the Korea Society of Computer and Information
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• v.16 no.8
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• pp.119-128
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• 2011

This paper introduces design space exploration of many-core processors that meet high performance and low power required by the beamforming algorithm of image signals of mobile ultrasound. For the design space exploration of the many-core processor, we mapped different number of ultrasound image data to each processing element of many-core, and then determined an optimal many-core processor architecture in terms of execution time, energy efficiency and area efficiency. Experimental results indicate that PE=4096 and 1024 provide the highest energy efficiency and area efficiency, respectively. In addition, PE=4096 achieves 46x and 10x better than TI DSP C6416, which is widely used for ultrasound image devices, in terms of energy efficiency and area efficiency, respectively.

• Journal of the Korea Society of Computer and Information
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• v.17 no.9
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• pp.103-112
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• 2012

Recently, the infrastructure to be connected to the internet is much provided, there is more and more need to connect electric or electronic products to the internet to monitor or control them remotely. However, most of the existing products lack the network interface, so it was very inconvenient to be connected to the internet. Therefore, this article designs and realizes the internet outlet allowing real-time scheduling that can control the power remotely on the internet by using the hardware TCP/IP processor. The realized product consumes low production cost because it can be realized by using the hardware TCP/IP processor and the 8-bit small microprocessor. In addition, the product can be used widely in both wired and wireless environments with a variety of user interface, including the dedicated control program which provides the environment configuration functions; embedded web service that enables the webpage to be saved on the external flash memory; Android smartphone application; motion recognition control environment that uses the OpenCV computer vision library, etc.

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.25-33
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• 2014

This paper proposes a power-efficient scheduling scheme that stochastically minimizes the power consumption of real-time tasks while meeting their deadlines on multicore processors. In the proposed scheme, uncertain computation amounts of given tasks are translated into probabilistic computation amounts based on their past completion amounts, and the mean power consumption of the translated probabilistic computation amounts is minimized with a finite set of discrete clock frequencies. Also, when system load is low, the proposed scheme activates a part of all available cores with unused cores powered off, considering the leakage power consumption of cores. Evaluation shows that the scheme saves up to 69% power consumption of the previous method.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.4
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• pp.85-90
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• 2014

We realized a wireless multiple integrated laser engagement system composed of personal area network using Zigbee. The wireless laser detector had function of analog signal processor, decoder and wireless communication. However, it should consume low power and be small and light in order to be attached to a soldier's body. The decoder was realized in software to be small and light. We induced low power consumption as reducing the load of system using a narrow band optical filter. The fabricated wireless laser detector functioned well in optically noisy environment. Although the communication to the player unit through the wireless personal area network was dependent on the attachment place it was perfectly worked with transmission power of -40.2dBm or more.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.1
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• pp.60-66
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• 2004

In order to analyze voltage, current electrical power, harmonic and so on of electrical load equipments, electrical power analysis by real measurement rather than mathematical modeling is necessary, and plan of countermeasure for efficient management, energy frugality and accident prevention of electrical equipments using it is possible Especially, electrical power analysis by real measurement is indispensable in order to consider countermove of harmonic occurred by nonlinear load So, in this paper, we developed DSP(Digital Signal Processor) based low price date aquisition system, and verified it's ability by performing measurement and analysis of electrical power and harmonic in the real power system.