• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.8
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• pp.1488-1494
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• 2008

This paper is to design and implement a low power noncoherent BFSK receiver intended for future deep space communication using Xilinx System generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital design for better efficiency and reliability. The receiver functions on one bit data processing and supports main data rate 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT and multiplication of twiddle factor for low power is substituted by rotators. The design and simulation of the receiver is carried out in Simulink then the Simulink model is translated to the hardware model to implement FPGA using Xilinx System Generator and to verify performance.

• Journal of Power Electronics
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• v.15 no.4
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• pp.1018-1025
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• 2015

This paper proposes a methodological scheme for the photovoltaic (PV) simulator design. With the advantages of a digital controller system, linear interpolation is proposed for precise fitting with higher computational efficiency. A novel control strategy that directly tackles two different duty cycles is proposed and implemented to achieve a full-range operation including short circuit (SC) and open circuit (OC) conditions. Systematic design procedures for both hardware and algorithm are explained, and a prototype is built. Experimental results confirm an accurate steady state performance under different load conditions, including SC and OC. This low power apparatus can be adopted for PV education and research with a limited budget.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.5
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• pp.12-19
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• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.1
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• pp.173-180
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• 2022

Approximate Computing is a promising method for designing hardware-efficient computing systems. Approximate multiplication is one of key operations used in approximate computing methods for high performance and low power computing. An approximate 4-2 compressor can implement hardware-efficient circuits for approximate multiplication. In this paper, we propose an approximate multiplier with low area and low power characteristics. The proposed approximate multiplier architecture is segmented into three portions; an exact region, an approximate region, and a constant correction region. Partial product reduction in the approximation region are simplified using a new 4:2 approximate compressor, and the error due to approximation is compensated using a simple error correction scheme. Constant correction region uses a constant calculated with probabilistic analysis for reducing error. Experimental results of 8×8 multiplier show that the proposed design requires less area, and consumes less power than conventional 4-2 compressor-based approximate multiplier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2B
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• pp.215-224
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• 2010

A container security device (CSD) monitors intrusions through the cargo door; it is a reduced function device that uses IEEE 802.15.4 with a beacon mode. However, in the beacon mode, the CSD consumes too much battery power in periodical idle listening and sensing trials. Moreover, the CSD cannot send the message to the CSD reader actively, and it makes big latency problem. Therefore, we propose a low-power CSD to reduce the unnecessary power consumption. The proposed CSD follows the requirements of the U.S. Department of Homeland Security, and reduces battery consumption through a power-efficient hardware design, a night-watch mechanism for low-power operation and low-power sensing to reduce unnecessary monitoring. And the CSD sends alert message to the CSD reader. Simulation results show that our CSD reduces battery consumption by over 70% through the night-watch mechanism and by approximately 80% through the low-power sensing. And the CSD can send the alert message to the remote CSD reader by over 94%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.888-894
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• 2015

This paper describes an efficient hardware design of Lightweight Encryption Algorithm (LEA) developed by National Security Research Institute(NSRI). The LEA crypto-processor supports for master key of 128-bit. To achieve small-area and low-power implementation, an efficient hardware sharing is employed, which shares hardware resources for encryption and decryption in round transformation block and key scheduler. The designed LEA crypto-processor was verified by FPGA implementation. The LEA core synthesized with Xilinx ISE has 1,498 slice elements, and the estimated throughput is 216.24 Mbps with 135.15 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.2
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• pp.361-370
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• 1997

In this paper, we designed POCSAG Signal Decoder to improve operating time in pager. We showed POCSAG Signal Pattern sent by transmitter and operation of this decoder. We also showed that the Pager using this decoder was equipped with Wide Area Signal Detection and designed the hardware which realizes this operation and implemented it with ASIC chip. As we inspected the function of the ASIC chip and tested the performance, we could find that the chip operated in low voltage and that power dissipation was low.

• Journal of Korea Society of Digital Industry and Information Management
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• v.14 no.3
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• pp.29-38
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• 2018

It is the approach of embedded system design that analyzes COS(Cut Out Switch) failure in the power distribution and an instantaneous breakdown of power distribution supply could cause the weakness of industrial competence and therefore we need to feed the stable power distribution with developing the technology of open-source embedded system. In this paper, we apply the LoRa technology which is the Internet of Things(IoT) protocol for low data rate, low power, low cost and long range sensor applications. We designed the hardware and software architecture setup and experimented the embedded system with network architecture and COS monitoring system including accelerometer for detecting the failure of distribution line and sensing the failure of its fuse holder by recognizing the variation and collision and afterwards sending the information to a gateway. With experimenting we designed the embedded platform for sensing the variation and collision according to the COS failure, monitoring its fuse holder status and transferring the information of states with LoRa technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.85-95
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• 2004

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.131-136
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MB-OFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MB-OFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.