• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제15권5호
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• pp.315-321
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• 2009

U-city 등에서 원격 디지털 수도 검침 시스템의 수요가 증가하고 있다. 디지털 수도 미터는 센서의 종류에 따라 다양한데 홀센서를 사용한 방식은 정밀도가 높다는 장점이 있으나 기존의 알고리즘은 전력소모가 큰 것이 단점이다. 본 논문에서는 정밀도를 유지하면서 저전력 소모를 추구하는 센싱 알고리즘을 제시한다. 우리의 방식은 물의 사용 여부를 정밀도는 떨어지나 전력소모가 작은 홀센서를 이용하여 센싱하는 것이다. 물이 사용되기 시작하면 정밀도가 높은 홀 센서를 사용하여 사용량을 계측한다. 우리의 알고리즘이 기존의 방식보다 전력소모를 2배 가량 줄일 수 있음을 분석을 통하여 보였다.

• Journal of information and communication convergence engineering
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• 제16권2호
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• pp.130-134
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• 2018

Wireless capsule endoscopy (WCE) is considered as recent technology for the detection cancer cells in the human digestive system. WCE sends the captured information from inside the body to a sensor on the skin surface through a wireless medium. In WCE, the design of low-power consumption devices is a challenging topic. In the Shannon-Nyquist sampling theorem, the number of samples should be at least twice the highest transmission frequency to reconstruct precise signals. The number of samples is proportional to the power consumption in wireless communication. This paper proposes compressive sensing as a method to reduce power consumption in WCE, by means of a trade-off between samples and reconstruction accuracy. The proposed scheme is validated under channel constraints, expressed as the realistic human body path loss. The results show that the proposed scheme achieves a significant reduction in WCE power consumption and achieves a faster computation time with low signal error reconstruction.

• International Journal of Contents
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• 제7권1호
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• pp.1-7
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• 2011

A new power control algorithm for wireless communication which can be applied to various near distance communications and USN/RFID systems is proposed. This technique has been applied and tested to lithium coin battery operated UHF/microwave transceiver systems to show extremely long communication life time without battery exchange. The power control algorithm is based on the dynamic prediction method of arrival time for incoming packet at the receiver. We obtain 16mA current consumption in the TX module and 20mA current consumption in the RX module. The advantage provided by this method compared to others is that both master transceiver and slave transceiver can be low power consumption system.

• ETRI Journal
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• 제25권5호
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• pp.288-296
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• 2003

In this study, we present a 260k color TFT LCD driver chip set that consumes only 5 mW in the module, which has exceptionally low power consumption. To reduce power consumption, we used many power-lowering schemes in the logic and analog design. A driver IC for LCDs has a built-in graphic SRAM. Besides write and read operations, the graphic SRAM has a scan operation that is similar to the read operation of one row-line, which is displayed on one line in an LCD panel. Currently, the embedded graphic memory is implemented by an 8-transistor leaf cell and a 6-transistor leaf cell. We propose an efficient scan method for a 6-transistor embedded graphic memory that is greatly improved over previous methods. The proposed method is implemented in a 0.22 ${\mu}m$ process. We demonstrate the efficacy of the proposed method by measuring and comparing the current consumption of chips with and without our proposed scheme.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제16권4호
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• pp.462-466
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• 2010

본 논문은 하드디스크와 NAND 플래시메모리를 동시에 사용하는 저장 시스템 환경에서 전력 소모를 최소화하는 버퍼 캐쉬 관리 기법을 제안한다. 저장장치별 전력 소모율과 입출력 연산 종류(읽기 또는 쓰기) 및 블록의 재참조 가능성(최근성 및 빈도)을 통합적으로 고려하는 버퍼 캐쉬 관리 기법의 설계로 저장 시스템의 전력 소모량을 평균 18.0%, 최대 58.9%까지 줄일 수 있음을 보인다.

• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.59-63
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• 2007

In this paper, a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• 한국멀티미디어학회논문지
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• 제19권7호
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• pp.1179-1187
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• 2016

Through the rapid development of latest hardware technology, high performance as well as miniaturized size is the essentials of embedded system to meet various requirements from the society. It raises possibilities of genuine realization of IoT environment whose size and battery must be considered. However, the limitation of battery persistency and capacity restricts the long battery life time for guaranteeing real-time system. To maximize battery life time, low power technology which lowers the power consumption should be highly required. Previous researches mostly highlighted improving one single type of memory to increase ones efficiency. In this paper, reversely, considering multiple memories to optimize whole memory system is the following step for the efficient low power embedded system. Regarding to that fact, this paper suggests the study of volatile memory, whose capacity is relatively smaller but much low-powered, and non-volatile memory, which do not consume any standby power to keep data, to maximize the efficiency of the system. By executing function in specific memories, non-volatile and volatile memory, the quantitative analysis of power consumption is progressed. In spite of the opportunity cost of all of theses extra works to locate function in volatile memory, higher efficiencies of both power and energy are clearly identified compared to operating single non-volatile memory.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.144-147
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• 2005

This paper is proposed an 8$\times$8 bit parallel multiplier for low power consumption. The 8$\times$8 bit parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing tile previous works, this circuit is reduced the power consumption rate of 8.2% and the power-delay-product of 11.1%. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.35$\{\mu}m$ standard CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권5호
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• pp.563-569
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• 2015

For some low-frequency applications such as power-related circuits, NEM relays have been known to show better performance than MOSFETs. For example, in a step-down charge pump circuit, the NEM relays showed much smaller layout area and better energy efficiency than MOSFETs. However, severe process variations of NEM relays hinder them from being widely used in various low-frequency applications. To mitigate the process-variation problems of NEM relays, in this paper, a new NEM-relay charge pump circuit with the self-adjustment is proposed. By self-adjusting a pulse amplitude voltage according to process variations, the power consumption can be saved by 4.6%, compared to the conventional scheme without the self-adjustment. This power saving can also be helpful in improving the power efficiency of the proposed scheme. From the circuit simulation of NEM-relay charge pump circuit, the efficiency of the proposed scheme is improved better by 4.1% than the conventional.

• 한국정보통신학회논문지
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• 제18권3호
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• pp.586-594
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• 2014

수중 통신 상에서 가장 중요한 요소는 한정된 전원을 보다 효율적으로 소모하여 운영 가능 시간을 최대화하는데 있다. 보다 효율적인 전압 소모를 위해 적용 가능한 기법으로는 동적 전압 스케일 기법이 있다. 해당 기법은 평상시에는 낮은 주파수로 동작하여 대기 전력을 최소화하며 복잡한 연산을 수행하는 경우에는 빠른 주파수로 계산함으로써 전체 소모되는 전력량을 줄인다. 복잡한 암호화 연산의 경우 빠른 주파수로 연산을 하는 것이 보다 효율적이다. 본 논문에서는 다양한 센서 상에서의 암호화 기법에 동적 전압 스케일 기법을 적용한 결과를 보여 줌으로써 수중 통신 상에서 적합한 저전력 암호화 방안에 대해 살펴본다.