• Journal of KIISE:Computer Systems and Theory
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• v.35 no.1
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• pp.18-29
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• 2008

NAND Flash memory has been growing popular storage device for the last years because of its low power consumption, fast access speed, shock resistance and light weight properties. However, it has the distinct characteristics such as erase-before-write architecture, asymmetric read/write/erase speed, and the limitation on the number of erasure per block. Due to these limitations, various Flash Translation Layers (FTLs) have been proposed to effectively use NAND flash memory. The systems that adopted the conventional FTL may result in severe performance degradation by the hot data which are frequently requested data for overwrite in the same logical address. In this paper, we propose a novel FTL algorithm called Adaptive Flash Translation Layer (AFTL) which uses sector mapping method for hot data and log-based block mapping method for cold data. Our system removes the redundant write operations and the erase operations by the separating hot data from cold data. Moreover, the read performance is enhanced according to sector translation that tends to use a few read operations. A series of experiments was organized to inspect the performance of the proposed method, and they show very impressive results.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.172-172
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• 2011

Anaerobic digestion(AD) has successfully been used for many applications that have conclusively demonstrated its ability to recycle biogenic wastes. AD has been successfully applied in industrial waste water treatment, stabilsation of sewage sludge, landfill management and recycling of biowaste and agricultural wastes as manure, energy crops. During AD, i.e. organic materials are decomposed by anaerobic forming bacteria and fina1ly converted to excellent fertilizer and biogas which is primarily composed of methane(CH4) and carbon dioxide(CO2) with smaller amounts of hydrogen sulfide(H2S) and ammonia(NH3), trace gases such as hydrogen(H2), nitrogen(N2), carbon monoxide(CO), oxygen(O2) and contain dust particles and siloxanes. The production and utilisation of biogas has several environmental advantages such as i)a renewable energy source, ii)reduction the release of methane to the atomsphere, iii)use as a substitute for fossil fuels. In utilisation of biogas, most of biogas produced from small scale plant e.g. farm-scale AD plant are used to provide as energy source for cooking and lighting, in most of the industrialised countries for energy recovery, environmental and safety reasons are used in combined heat and power(CHP) engines or as a supplement to natural. In particular, biogas to use as vehicle fuel or for grid injection there different biogas treatment steps are necessary, it is important to have a high energy content in biogas with biogas purification and upgrading. The energy content of biogas is in direct proportion to the methane content and by removing trace gases and carbon dioxide in the purification and upgrading process the energy content of biogas in increased. The process of purification and upgrading biogas generates new possibilities for its use since it can then replace natural gas, which is used extensively in many countries, However, those technologies add to the costs of biogas production. It is important to have an optimized purification and upgrading process in terms of low energy consumption and high efficiency giving high methane content in the upgraded gas. A number of technologies for purification and upgrading of biogas have been developed to use as a vehicle fuel or grid injection during the passed twenty years, and several technologies exist today and they are continually being improved. The biomethane which is produced from the purification and the upgrading process of biogas has gained increased attention due to rising oil and natural gas prices and increasing targets for renewable fuel quotes in many countries. New plants are continually being built and the number of biomethane plants was around 100 in 2009.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.5
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• pp.199-212
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• 2008

Software simulation has been widely used for the design and application development of a large-scale wireless sensor network. The degree of details of the simulation must be high to verify the behavior of the network and to estimate its execution time and power consumption of an application program as accurately as possible. But, as the degree of details becomes higher, the simulation time increases. Moreover, as the number of sensor nodes increases, the time tends to be extremely long. We propose an optimal-synchronous parallel discrete-event simulation method to shorten the time in a large-scale sensor network simulation. In this method, sensor nodes are partitioned into subsets, and each PC that is interconnected with others through a network is in charge of simulating one of the subsets. Results of experiments using the parallel simulator developed in this study show that, in the case of the large number of sensor nodes, the speedup tends to approach the square of the number of PCs participating in the simulation. In such a case, the ratio of the overhead due to parallel simulation to the total simulation time is so small that it can be ignored. Therefore, as long as PCs are available, the number of sensor nodes to be simulated is not limited. In addition, our parallel simulation environment can be constructed easily at the low cost because PCs interconnected through LAN are used without change.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.1
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• pp.585-591
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• 2017

Turbocharging is widely used in diesel and gasoline engines as an effective way to reduce fuel consumption. But turbochargers have turbo-lag due to mechanical friction losses. Bearing friction losses are a major cause of mechanical friction losses and are particularly intensified in the lower speed range of the engine. Current turbochargers mostly use oil bearings (two journal bearings and one thrust bearing). In this study, we focus on the bearing friction in the lower speed range. Experimental equipment was made using a drive motor, load cell, magnetic coupling, and oil control system. We measured the friction losses of the turbocharger while considering the influence of the rotation speed, oil temperature, and pressure. The friction power losses increased exponentially when the turbocharger speed increased.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.78-87
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• 2013

NAND flash memory has been widely used as a storage medium in mobile devices, PCs, and workstations due to its advantages such as low power consumption, high performance, and random accessability compared to a hard disk drive. However, NAND flash cannot support in-place update so that it is mandatory to erase the entire block before overwriting the corresponding page. In order to overcome this drawback, flash storages need a software support, named Flash Translation Layer. However, as the high performance mass NAND flash memory is getting widely used, the size of mapping tables is increasing more than the limited DRAM size. In this paper, we propose an adaptive mapping information caching algorithm based on page mapping to solve this DRAM space shortage problem. Our algorithm uses a mapping information caching scheme which minimize the flash memory access frequency based on the analysis of several workloads. The experimental results show that the proposed algorithm can increase the performance by up to 70% comparing with the previous mapping information caching algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.85-96
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• 2000

It is necessary that fully differential operational amplifier circuit should drive an external load in the VLSI design such as SCF(Switched Capacitor Filter), D/A Converter, A/D Converter, Telecommunication Circuit and etc. The conventional CMOS operational amplifier circuit has many problems according to CMOS technique. Firstly, Capacity of large loads are not able to operate well. The problem can be solve to use class AB stages. But large loads are operate a difficult, because an element of existing CMOS has a quadratic functional relation with input and output voltage versus output current. Secondly, Whole circuit of dynamic range decrease, because a range of input and output voltages go down according as increasing of intergration rate drop supply voltage. The problem can be improved by employing fully differential operational amplifier using differential output stage with wide output swing. In this paper, we proposed new current mirror has large output impedance and good current matching with input an output current and compared with characteristics for operational amplifier using cascoded current mirror. To obtain large output swing and low power consumption we suggest a fully differential operational amplifier. The circuit employs an output stage composed new current mirror and two amplifier stage. The proposed circuit is layout and circuit of capability is inspected through simulation program(SPICE3f).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.41-50
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• 2009

The flash memory has many advantages such as low power consumption, strong shock resistance, fast I/O and non-volatility. And it is increasingly used in the mobile storage device. Many researchers are studying the YAFFS, NAND flash file system, which is widely used in the embedded device. However, the existing YAFFS has two problems. First, it takes long time to mount the YAFFS file system because it scans whole spare areas in all pages. Second, the cleaning policy of the YAFFS does not consider the wear-leveling so that it cannot guarantee the duration of data completely. In order to solve these problems, this paper proposes a new content-based YAFFS that consists of a mounting time reduction technique and a content-cleaning policy by using content-based block management. The proposed method only scans partial spare areas of some special pages and provides the block swapping which enables the wear-leveling of data blocks. We performed experiments to compare the performance of the proposed method with those of the JFFS2 system and YAFFS system. Experimental results show that the proposed method reduces the average mounting time by 82.2% comparing with JFFS2 and 42.9% comparing with YAFFS. Besides, it increases the life time of the flash memory by 35% comparing with the existing YAFFS whereas no overheat is added.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.2
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• pp.25-34
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• 2010

This paper proposed a high-speed voltage-controlled ring-oscillator(VCRO) using a frequency doubling technique. The design of the proposed oscillator has been based on TSMC 0.18um 1.8V CMOS technology. The frequency doubling technique is achieved by AND-OR operations with 4 signals which have $90^{\circ}$ phase difference one another in one cycle. The proposed technique has been implemented using a 4-stage differential oscillator compose of differential latched inverters and NAND gates for AND and OR operations. The differential ring-oscillator can generate 4 output signals, which are $90^{\circ}$ out-of-phase one another, with low phase noise. The ANP-OR operations needed in the proposed technique are implemented using NAND gates, which is more area-efficient and provides faster switching speed than using NOR gates. Simulation results show that the proposed, VCRO operates in the frequency range of 3.72 GHz to 8 GHz with power consumption of 4.7mW at 4GHz and phase noise of ~-86.79dBc/Hz at 1MHz offset. Therefore, the proposed oscillator demonstrates superior performance compared with previous high-speed voltage-controlled ring-oscillators and can be used to build high-performance frequency synthesizers and phase-locked loops for radio-frequency applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.61-69
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• 2010

In this paper, an 1.2V 8b 800MSPS A/D Converter(ADC) with an odd number of folding block to overcome the asymmetrical boundary-condition error is described. The architecture of the proposed ADC is based on a cascaded folding architecture using resistive interpolation technique for low power consumption and high input frequency. The ADC employs a novel odd folding block to improve the distortion of signal linearity and to reduce the offset errors. In the digital block, furthermore, we use a ROM encoder to convert a none-$2^n$-period code into the binary code. The chip has been fabricated with an $0.13{\mu}m$ 1P6M CMOS technology. The effective chip area is $870{\mu}m\times980{\mu}m$. SNDR is 44.84dB (ENOB 7.15bit) and SFDR is 52.17dBc, when the input frequency is 10MHz at sampling frequency of 800MHz.

• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.1-10
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• 2011

There are the large overhead of block erase and page write operations in NAND flash memory, though it has low power consumption, cheap prices and a large storage. Due to the physical characteristics of NAND flash memory, overwrite operations are not permitted at the same location, so rewriting operation require after erase operation. it cause performance decrease of NAND flash memory. Using SRAM buffer in traditional NAND flash memory, it can not only reduce effective write operation but also guarantee fast memory access time. In this paper, we proposed the small SRAM buffer management system for reducing overhead of NAND flash memory, that is, erase and write operations. The proposed buffer system in a NAND flash memory consists of two parts, i.e., a fully associative temporal buffer with the small fetching block size and a fully associative spatial buffer with the large fetching block size. The temporal buffer have small fetching blocks that referenced from spatial buffer. When it happen write operations or erase operations in NAND flash memory, the related fetching blocks in temporal buffer include a page or a block are written in NAND flash memory at the same time. The writing and erasing counts in NAND flash memory can be reduced. According to the simulation results, although we have high miss ratios, write and erase operations can be reduced approximatively 58% and 83% respectively. Also the average memory access times are improved about 84% compared with the fully associative buffer with two sizes.