• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1157-1160
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• 2003

We proposed a study on optimal clock period selection algorithm for low power RTL design. The proposed algorithm use the way of maintaining the throughput by reducing supply voltage after improve the system performance in order to minimize the power consumption. In this paper, it select the low power to use pipeline in the transformation of architecture. Also, the algorithm is important the clock period selection in order to maximize the resource sharing. however, it execute the optimal clock period selection algorithm.

• ETRI Journal
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• v.32 no.3
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• pp.457-459
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• 2010

A low-power down-sampling mixer in a low-power digital 65 nm CMOS technology is presented. The mixer consumes only 830 ${\mu}W$ at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The measured gain is (19 ${\pm}$1 dB) at frequencies between 100 MHz and 3 GHz. An IIP3 of -5.9 dBm is achieved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4A
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• pp.365-372
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• 2007

In IEEE 802.11b wireless network, stations synchronize themselves to the beacons periodically sent by the access point(AP) when they are running in low power mode. In case of missing beacon due to noise or traffic from neighboring wireless network stations must be awake until they get the next beacon, which causes energy consumption in stations. In this paper, we propose a scheme searching next beacon consuming little energy. The problems of missing beacon in low power mode of IEEE 802.11b wireless interface are described and a new method to reduce energy consumption is proposed. The proposed method is simulated with the network simulator, ns2, and compared with the low power mode of the IEEE 802.11b. The result measured in terms of station's wakeup time shows some enhancement in energy consumption when some errors occur in receiving frames.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.479-481
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• 2006

This paper describes a 2.5V, 320MHz low-noise and low-power Phase Locked Loop(PLL) using a noise-rejected Voltage Controlled ring Oscillator(VCO) fabricated in a TSMC 0.25um CMOS technology. In order to improve the power consumption and oscillation frequency of the PLL, The VCO consist of three-stage fully differential delay cells that can obtain the characteristic of high speed, low power and low phase noise. The VCO operates at 7MHz -670MHz. The oscillator consumes l.58mA from a 320MHz frequency and 2.5V supply. When the PLL with fully-differential ring VCO is locked 320MHz, the jitter and phase noise measured 26ps (rms), 157ps (p-p) and -97.09dB at 100kHz offset. We introduce and analysis the conditions in which ring VCO can oscillate for low-power operation.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.561-564
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• 2004

The motion estimation which requires huge computation consumes large power in a video encoder. Although a number of fast-search algorithms are proposed to reduce the power consumption, the smaller the computation, the worse the performance they have. In this paper, we propose an architecture that a low energy management scheme can be applied with several fast-search algorithm. In addition. we show that ECVH, a software scheduling scheme which dynamically changes the search algorithm, the operating frequency, and the supply voltage using the remaining slack time within given power-budget, can be applied to the architecture, and show that the power consumption can be reduced.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.37-45
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• 1998

A 32-b self-timed parallel carry look-ahead adder (PCLA) designed for 0.5.mum. single threshold low power CMOS technology is demonstrated to operate with 2.7nsec delay at 8mW under 1V power supply. Compared to static PCLA and DPL adder, the self-timed PCLA designed with NORA logic provides the best performance at the power consumption comparable to other adder structures. The wave pipelined clock control play a crucial role in achieving the low power, high performance of this adder by eliminating the unnecessary power consumption due to the short-circuit current during the precharge phase. Th enoise margin has been improved by adopting the physical design of staic CMOS logic structure with controlled transistor sizes.

• Proceedings of the KOSOMBE Conference
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• v.1993 no.11
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• pp.33-35
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• 1993

A new low-power, high-order optimization scheme to design surface gradient coils (SGC) is proposed for magnetic resonance imaging (MRI). Although previous SGCs have been designed and constructed just to get strong linear gradients, this paper proposes more systematic ways of SGC design by minimizing electrical power consumption in the gradient coil and by removing unnecessary high-order field distortions in the imaging region. By assuming continuous current flow on the coil surface which may be or may not be planar, power consumption in the coil is minimized. According to the simulation results, the SGC designed by using the proposed scheme seems to produce much more uniform linear gradient field using less electrical power compared to the previously proposed SGCs.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.10 no.4
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• pp.135-142
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• 2011

This paper proposes a performance evaluation method for power consumption of set-top box (STB) stand-by mode transition schemes. A stand-by mode transition scheme characterizes the timing of mode transition. The timing of mode transition affects the duration of stand-by mode operation, and the power consumptions of STB as well. Recently a fast stand-by mode transition scheme (FMT) has been proposed based on user input for selecting the device to be connected to TV. In this paper, we evaluate power consumption of FMT and a conventional mode transition scheme. For the computation of the duration of stand-by mode operation, the user input events are modeled as Poisson process. Simulation results based on the modeling reveals that the proposed scheme is more effective in power saving than the conventional scheme by up to 30%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6B
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• pp.641-647
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• 2009

This paper proposes an improved predictive dynamic power management (DPM) scheme and a task scheduling algorithm to reduce unnecessary power consumption in embedded systems. The proposed algorithm performs pre-scheduling to minimize unnecessary power consumption. The proposed predictive DPM utilizes a scheduling library provided by the system to reduce computation overhead. Experimental results show that the proposed algorithm can reduce power consumption by 22.3% on the average comparing with the LLF algorithm for DPM-enable system scheduling.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.6
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• pp.1419-1435
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• 2015

In this study an active RFID system of low power consumption is proposed, for which we improved the tag collection algorithm of ISO/IEC 18000-7 standard and significantly reduced the tag collection time. We classified the type of power consumption according to the operating mode of active RFID and proposed the method which can accurately estimate battery life time. By calculating the power consumptions of proposed and current methods, we can compare the battery life times of both methods. Through this analysis we can demonstrate the superiority of the proposed method in battery life time.