• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.845-849
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• 2005

Quick-Response Liquid Powder Display ($QR-LPD^{(R)}$) is a promising device for ultra-low-power applications. Several driving methods for this display were investigated in terms of image quality and power consumption. The power consumed both in a panel and in the output circuits of driver LSIs was evaluated by analog circuit simulation and discussed.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.347-348
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• 2007

Most of the power consumption of a LCD TV is form the back light unit. Therefore, technoledge for decreasing the power consumption of the backlight unit is crucial for LCD Tvs. This research suggests a method of decreasing the power comsumption of LCD TV by analyzing the image's RGB info to dimm partitioned backlights independently.

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.243-248
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• 2008

This paper proposes a low-power carry look-ahead adder using multi-threshold voltage CMOS. The designed adder is compared with conventional CMOS adder. The propagation delay time is reduced by using low-threshold voltage transistor in the critical path. Also, the power consumption is reduced by using high-threshold voltage transistor in the shortest path. The other logic block is implemented with normal-threshold transistor. Comparing with the conventional CMOS circuit, the proposed circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.5
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• pp.193-197
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• 2017

In this paper, we present a low-power delta-sigma based digital frequency synthesizer with high frequency resolution for bio sensor networks. Biomedical radio-frequency (RF) transceivers require miniaturized forms with a long battery life and low power consumption. For the technology scaling, digital circuits have become preferable compared to analog circuits because of the aggressive cost, size, flexibility, and repeatability. Therefore, the digital circuits based on standard-cell library are used to reduce a power consumption. Additionally, a delta-sigma is used for making fractional frequency tuning range. From the simulation, we confirmed that proposed scheme has good performance in accordance with power and frequency resolution.

• The Journal of the Korea Contents Association
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• v.10 no.12
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• pp.10-17
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• 2010

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using $0.13-{\mu}m$ CMOS process under 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.81-90
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• 2004

The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique . based on m-block partition is introduced in this paper. By the m-block partition algorithm, the dependencies among groups of state variables are minimized and switching activity is further reduced by assigning the codes of the states in the same group considering the state transition probability among the states. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on state variables. It is inherently contradictory problem to optimize the testability and power consumption simultaneously, however our new state assignment technique is able to achieve high fault coverage with less number of scan nfp flops by reducing the number of feedback cycles while the power consumption is kept low upon the low switching activities among state variables. Experiment shows drastic improvement in testabilities and power dissipation for benchmark circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.39-46
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• 2012

The newly designed sense amplifier in this paper has rail-to-rail input range achieving low power consumption. Reducing static power consumption generated due to DC path to ground is key element for low power consumption in this paper. The proposed sense amplifier performs power-saving operation using negative feedback circuit that controls the current flow with the newly added PMOS input terminal. As a simulation result, the proposed sense amplifier consumed about over 50 % efficiency of the average power consumed by the typical Rail-to-Rail sense amplifier.

• Journal of Sensor Science and Technology
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• v.26 no.3
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• pp.209-213
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• 2017

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of high area overhead and high power consumption. This paper proposes a new NCL gate based on power gating structure. The proposed $4{\times}4$ NCL multiplier based on power gating structure is compared to the conventional NCL $4{\times}4$ multiplier and MTNCL(Multi-Threshold NCL) $4{\times}4$ multiplier in terms of speed, power consumption, energy and size using PTM 45 nm technology.

• Journal of IKEEE
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• v.22 no.3
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• pp.862-865
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• 2018

The proposed scheme minimizes the Idle time under the residual energy of the sensor node to adjust the Sleep-Wakeup period and minimize unnecessary energy consumption. It is The proposed scheme minimizes the Idle time under the residual energy of the sensor node to adjust the Sleep-Wakeup period and minimize unnecessary energy consumption. It is an important process to control the Application Packet Framework including the PHY and the MAC layer at each node's Idle time with the Idle time mechanism state before the proposed function is executed. The Current Control Level of the Report Attribute is fixed at one sending / receiving node where power consumption can occur, by changing Sleep-Wakeup time, the low power consumption efficiency was improved while satisfying the transmission requirement of the given delay time constraint.

• Journal of IKEEE
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• v.13 no.3
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• pp.39-46
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• 2009

Wireless sensor networks consist of small, autonomous devices with wireless networking capabilities. In order to further increase the applicability in real world applications, minimizing energy consumption is one of the most critical issues. Therefore, accurate energy model is required for the evaluation of wireless sensor networks. In this paper we analyze the power consumption for wireless sensor networks. To develop the power consumption model, we have measured the power characteristics of commercial Kmote node based on TelosB platforms running TinyOS. Based on our model, the estimated lifetime of a battery powered sensor node can use about 6.9 months for application of human detection using PIR sensors. This result indicates that sensor nodes can be used in a monitoring system for elderly living alone.