• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.48 no.4
• /
• pp.1-5
• /
• 2011

We present the implementation of MAC system for MBOA UWB SoC. The implemented MBOA MAC algorithm is not master control mechanism, but distributed network mechanism. Therefore, mesh network can be easily constructed because MAC consists of distributed network and administrates network. The ARM926EJ with cache is adopted for high performnace and AMBA bus is applied for system design and reuse. In addition, the system operating clock management algorithm is implemented for low power consumption. The dedicated DMA for MAC is designed between the system memory buffer and MAC hardware, and the dedicated DMA for USB 2.0 is also implemented between system memory buffer and host for high data transaction.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.42 no.7
• /
• pp.586-593
• /
• 2014

The CNUSAIL-1 project aims to develop and operate a 3U-sized cube satellite with solar sail mechanism. The primary mission is to successfully deploy the solar sail in a low earth orbit, and the secondary mission is to collect the scientific data for the effect of the solar sail deployment and operation on orbit maneuver and attitude change of the cube satellite. For this, the bus system will collect and transmit the dynamic data of the satellite and the visual images of the solar sail operation. This paper describes solar sail mission and conceptual design of CNUSAIL-1. The actuation/operation of the solar sail and the bus system are preliminarily designed in terms of attitude control system, communication system, electrical power system, command and data handling system, structure and thermal control system is designed.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.9
• /
• pp.201-208
• /
• 2013

In this paper, we studied on improvement for radiated EMI of USB power line of cable. it is made by using wireless video access point system for confirming the phenomenon of radiated EMI from cable. then, we make sure that the limit exceed through the initial measurement of radiated EMI limit criteria in comparison to about 3 [dBuV/m]~15 [dBuV/m]. after that we confirmed the resonance in power line of cable through measurement of s-parameters. so, we confirmed the relation radiated EMI and power line of cable resonance and we reduced radiated EMI in power line of cable through a capacitor and low pass-band filter using the technique of power networks management. in conclusion, we suggested how to reduce power line of cable resonance applied for the improved method. and we confirmed that suggested reduction method is suitable through testing radiated EMI. the result of radiated EMI reduction limit criteria 40[dBuV/m]~47[dBuV/m] in comparison to about 3 [dBuV/m]~20 [dBuV/m].

• Smart Structures and Systems
• /
• v.2 no.2
• /
• pp.115-126
• /
• 2006

The Terra-Scope system is an affordable 4-D down-hole seismic monitoring system based on independent, microprocessor-controlled sensor Pods. The Pods are nominally 50 mm in diameter, and about 120 mm long. They are expected to cost approximately $6000 each. An internal 16-bit, extremely low power MCU controls all aspects of instrumentation, eight programmable gain amplifiers, and local signal storage. Each Pod measures 3-D acceleration, tilt, azimuth, temperature, and other parametric variables such as pore water pressure and pH. Each Pod communicates over a standard digital bus (RS-485) through a completely web-based GUI interface, and has a power consumption of less than 400 mW. Three-dimensional acceleration is measured by pure digital force-balance MEMS-based accelerometers. These accelerometers have a dynamic range of more than 115 dB and a frequency response from DC to 1000 Hz with a noise floor of less than $30ng_{rms}/{\surd}Hz$. Accelerations above 0.2 g are measured by a second set of MEMS-based accelerometers, giving a full 160 dB dynamic range. This paper describes the system design and the cooperative shared-time scheduler implemented for this project. Restraints accounted for include multiple data streams, integration of multiple free agents, interaction with the asynchronous world, and hardened time stamping of accelerometer data. The prototype of the device is currently undergoing evaluation. The first array will be installed in the spring of 2006.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.444-448
• /
• 2005

This paper presents a developing procedure of the CAN-based real-time simulator for car body control, aiming at replacing the actual W/H (Wiring Harness) and J/B(Junction Box) couple eventually. The CAN protocol, as one kind of field-bus communication, defines the lowest 2 layers of the ISO/OSI standard, namely, the physical layer(PL) and the data link layer(DLL), for which the CSMA/NBA protocol is generally adopted. For CPU, two PIC18Fxx8x's are used because of their built-in integration of CAN controller, large internal FLASH memory (48K or 64K), and their costs. To control J/B's and actuators, 2 controller boards are separately implemented, between which CAN lines communicate through CAN transceivers MCP255. A power motor for washing windshield, 1 door lock motor, and 6 blink lamps are chosen for actuators of the simulator for the first stage. For the software architecture, a polling method is used for the fast global response time despite its slow individual response time. To improve the individual response time and to escape from some eventual trapped-function loops, High/Low ports of the CPU are simply used, which increases the stability of the actuator modules. The experimental test shows generally satisfactory results in normal transmitting / receiving function and message trace function. This simulator based on CAN shows a promising usefulness of lighter, more reliable and intelligent distributed body control approach than the conventional W/H and J/B couple. Another advantage of this approach lies in the distributed control itself, which gives better performance in hard real-time computing than centralized one, and in the ability of integrating different modules through CAN.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.5
• /
• pp.922-930
• /
• 2009

An optimized PWM switching strategy for an induction motor voltage control is developed and demonstrated. Space vector modulation in voltage source inverter offers improved DC-bus utilization and reduced commutation losses and has been therefor recognized the preferred PWM method especially in case of digital implementation. An optimized PWM switching strategy for an induction motor voltage control consists of switching between the two active and one zero voltage vector by using the proposed optimal PWM algorithm. The preferred switching sequence is defined as a function of the modulation index and period of a carrier wave. The sequence is selected by using the inverter switching losses and the current ripple as the criteria. For low and medium power application, the experimental results indicate that good dynamic response and reduced harmonic distortion can be achieved by increasing switching frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.9
• /
• pp.1-6
• /
• 2010

H.264 video coding standard is widely used due to the high compression rate and quality. H.264 decoders usually have pipeline architecture by a macroblock or a $4{\times}4$ sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and the requirement of high data bandwidth and high performance processing units. We propose adaptive pipeline architecture for H.264 decoders for efficient decoding and lower the requirement of the bandwidth for the memory bus. Parameters and coefficients are delivered using hand-shaking communication through dedicated interconnections and frame pixel data are transferred using AMBA AHB network. The processing time of each block is variable depending on the characteristics of images, and the processing units start to work whenever they are ready. An H.264 decoder is designed and implemented using the proposed architecture to verify the operation using an FPGA.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.1
• /
• pp.14-21
• /
• 2011

A 10b 500MS/s $0.13{\mu}m$ CMOS ADC is proposed for 4G wireless communication systems such as a LTE-Advanced and SDR The ADC employs a calibration-free single-channel folding architecture for low power consumption and high speed conversion rate. In order to overcome the disadvantage of high folding rate, at the fine 7b ADC, a cascaded folding-interpolating technique is proposed. Further, a folding amplifier with the folded cascode output stage is also discussed in the block of folding bus, to improve the bandwidth limitation and voltage gain by parasitic capacitances. The chip has been fabricated with $0.13{\mu}m$ 1P6M CMOS technology, the effective chip area is $1.5mm^2$. The measured results of INL and DNL are within 2.95LSB and l.24LSB at 10b resolution, respectively. The SNDR is 54.8dB and SFDR is 63.4dBc when the input frequency is 9.27MHz at sampling frequency of 500MHz. The ADC consumes 150mW($300{\mu}W/MS/s$) including peripheral circuits at 500MS/s and 1.2V(1.5V) power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.6 s.348
• /
• pp.9-17
• /
• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• Journal of the Korean Vacuum Society
• /
• v.16 no.6
• /
• pp.483-488
• /
• 2007

Current feeder system (CFS) for Korea superconducting tokamak advanced research(KSTAR) project plays a role to interconnect magnet power supply (MPS) and superconducting (SC) magnets through the normal bus-bar at the room temperature(300 K) environment and the SC bus-line at the low temperature (4.5 K) environment. It is divided by two systems, i.e., toroidal field system which operates at 35 kA DC currents and poloidal field system wherein 20$\sim$26 kA pulsed currents are applied during 350 s transient time. Aside from the vacuum system of main cryostat, an independent vacuum system was constructed for the CFS in which a roughing system is consisted by a rotary and a mechanical booster pump and a high vacuum system is developed by four cryo-pumps with one dry pump as a backing pump. A self interlock and its control system, and a supervisory interlock and its control system are also established for the operational reliability as well. The entire CFS was completely tested including the reliability of local/supervisory control/interlock, helium gas leakage, vacuum pressure, and so on.