• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.10
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• pp.2572-2576
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• 2009

The wafer prober is used in mass production process of semiconductor chips. The chuck in wafer prober must have a uniform temperature distribution when the chuck is heated or cooled. The temperature distribution of prober chuck is measured by using a thermocouple when the chuck is cooled. The temperature distribution is also calculated by using a CFD program, FLUENT. The measured temperature and calculated temperature show similar distributions. A modified coolant circuit distribution for the improving temperature uniformity is suggested based on the numerical analysis results.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.119-123
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• 2001

In this paper, a new structure and fabrication method for the wafer level package(WLP) is presented. A packaged VLSI chip is encapsulated by a parylene(which is a low k material) layer as a dielectric layer and is molded by SUB photo-epoxy with dielectric constant of 3.0 at 100 MHz. The electrical parameters (R, L, C) of package traces are extracted by using the Maxwell 3-D simulator. Based on HSPICE simulation results, the proposed wafer level package can operate for frequencies up to 20GHz.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.180-180
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• 2000

Plasma source ion implantation is a new doping technique for the formation of shallow junction with the merits of high dose rate, low-cost and minimal wafer charging damage. In plasma source ion implantation process, the wafer is placed directly in the plasma of the appropriate dopant ions. Negative pulse bias is applied to the wafer, causing the dopant ions to be accelerated toward the wafer and implanted below the surface. In this work, inductively couples plasma was generated by anodized Al antenna that was located inside the vacuum chamber. The outside wall of Al chamber was surrounded by Nd-Fe-B permanent magnets to confine the plasma and to enhance the uniformity. Before implantation, the wafer was pre-sputtered using DC bias of 300B in Ar plasma in order to eliminate the native oxide. After cleaning, B2H6 (5%)/H2 plasma and negative pulse bias of -1kV to 5 kV were used to form shallow p+/n junction at the boron dose of 1$\times$1015 to 5$\times$1016 #/cm2. The as-implanted samples were annealed at 90$0^{\circ}C$, 95$0^{\circ}C$ and 100$0^{\circ}C$during various annealing time with rapid thermal process. After annealing, the sheet resistance and the junction depth were measured with four point probe and secondary ion mass spectroscopy, respectively. The doping uniformity was also investigated. In addition, the electrical characteristics were measured for Schottky diode with a current-voltage meter.

• Tribology and Lubricants
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• v.35 no.6
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• pp.323-329
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• 2019

Sapphire is currently used as a substrate material for blue light-emitting diodes (LEDs). The market for sapphire substrates has expanded rapidly as the use of LEDs has extended into various industries. However, sapphire is classified as one of the most difficult materials to machine due to its hardness and brittleness. Recently, a lap-grinding process has been developed to combine the lapping and diamond mechanical polishing (DMP) steps in a single process. This paper studies, the effect of wafer surface roughness on the chemical mechanical polishing (CMP) process by pressure and abrasive concentration in the lap-grinding process of a sapphire wafer. In this experiment, the surface roughness of a sapphire wafer is measured after lap-grinding by varying the pressure and abrasive concentration of the slurry. CMP is carried out under pressure conditions of 4.27 psi, a plate rotation speed of 103 rpm, head rotation speed of 97 rpm, and slurry flow rate of 170 ml/min. The abrasive concentration of the CMP slurry was 20wt, implying that the higher the surface roughness after lapgrinding, the higher the material removal rate (MRR) in the CMP. This is likely due to the real contact area and actual contact pressure between the rough wafer and polishing pad during the CMP. In addition, wafers with low surface roughness after lap-grinding show lower surface roughness values in CMP processes than wafers with high surface roughness values; therefore, further research is needed to obtain sufficient surface roughness before performing CMP processes.

• Journal of the Korean Ceramic Society
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• v.29 no.4
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• pp.273-282
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• 1992

The effects of intrinsic and extrinsic gettering on the formation of microdefects in the wafer and on the electrical performance at near-surfaces of three different oxygen-bearing Czochralski silicon single crystal wafers were investigated by varying the combinations of the pre-heat treatments and the phosphorus diffusion through the back-surface of the wafers. The wafers which had less than 10.9 ppma of oxygen formed no gettering zones irrespective of any pre-heat treatments, while the wafers which had more than 14.1 ppma of oxygen and were treated by Low+High pre-heat treatments generated the gettering zone comprising oxygen precipitates, staking faults, and dislocation loops. The effects of extrinsic gettering by phosphorus diffusion were evident in all samples such that the minority carrier lifetimes were increased and junction leakage currents were decreased. However, the total gettering effects among the different pre-heat treatments did not necessarily correspond to the gettering structure revealed by synchrotron radiation section topograph.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.12
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• pp.1039-1044
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• 2002

Film Bulk Acoustic Resonator (FBAR) using thin piezoelectric films can be made as monolithic integrated devices with compatibility to semiconductor process, leading to small size, low cost and high Q RF circuit elements with wide applications in communications area. This paper presents an MMIC compatible suspended FBAR using SOI micromachining. It is possible to make a single crystal silicon membrane using a SOI wafer In fabricating active devices, SOI wafer offers advantage which removes the substrate loss. FBAR was made on the 12㎛ silicon membrane. Electrode and Piezoelectric materials were deposited by RF magnetron sputter. The maximum resonance frequency of FBAR was shown at 2.5GHz range. The reflection loss, K$^2$$\_$eff/, Q$\_$serise/ and Q$\_$parallel/ in that frequency were 1.5dB, 2.29%, 220 and 160, respectively.

• Journal of the Korean Vacuum Society
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• v.14 no.2
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• pp.91-96
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• 2005

The silicon-on-insulator (SOI) wafer fabrication technique has been developed by using ion-cut process, based on proton implantation and wafer bonding techniques. It has been shown by SRIM simulation that 65keV proton implantation is required for a SOI wafer (200nm SOI, 400nm BOX) fabrication. In order to investigate the optimum proton dose and primary annealing condition for wafer splitting, the surface morphologic change has been observed such as blistering and flaking. As a result, effective dose is found to be in the $6\~9\times10^{16}\;H^+/cm^2$ range, and the annealing at $550^{\circ}C$ for 30 minutes is expected to be optimum for wafer splitting. Direct wafer bonding is performed by joining two wafers together after creating hydrophilic surfaces by a modified RCA cleaning, and IR inspection is followed to ensure a void free bonding. The wafer splitting was accomplished by annealing at the predetermined optimum condition, and high temperature annealing was then performed at $1,100^{\circ}C$ for 60 minutes to stabilize the bonding interface. TEM observation revealed no detectable defect at the SOI structure, and the interface trap charge density at the upper interface of the BOX was measured to be low enough to keep 'thermal' quality.

• New & Renewable Energy
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• v.4 no.2
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• pp.68-73
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• 2008

It is very important that constitution of good hetero-junction interface with a high quality amorphous silicon thin films on very cleaned c-Si wafer for making high efficiency hetero-junction solar cells. For achieving the high efficiency solar cells, the inspection and management of c-Si wafer surface conditions are essential subjects. In this experiment, we analyzed the c-Si wafer surface very sensitively using Spectroscopic Ellipsometer for < ${\varepsilon}2$ > and u-PCD for effective carrier life time, so we accomplished < ${\varepsilon}2$ > value 43.02 at 4.25eV by optimizing the cleaning process which is representative of c-Si wafer surface conditions very well. We carried out that the deposition of high quality hydrogenated silicon amorphous thin films by RF-PECVD systems having high density and low crystallinity which are results of effective medium approximation modeling and fitting using spectroscopic ellipsometer. We reached the cell efficiency 12.67% and 14.30% on flat and textured CZ c-Si wafer each under AM1.5G irradiation, adopting the optimized cleaning and deposition conditions that we made. As a result, we confirmed that spectroscopic ellipsometry is very useful analyzing methode for hetero-junction solar cells which need to very thin and high quality multi layer structure.

• IE interfaces
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• v.18 no.3
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• pp.234-246
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• 2005

A silicon wafer is a highly customized product made to the individual order varying its electrical and physical characteristics. Therefore, it has distinctive supply chain structure that is different from highly standardized commodity product. For high-volume/high-standardization product, it is general that a main stream of information flow initiated by the production planning of the manufacturers is usually directed to push both ways in a supply chain: upstream to the suppliers and downstream to the customers. Contrastingly, for low-volume/high-customization product, the information flow triggered by the fluctuating customer demand usually propagates upward to the suppliers through the manufacturers. Furthermore, for R &D based hi-technology product like silicon wafer, the interactive information feedback mechanism between manufacturer and customer, which is essential to the new product development process, is to be embedded in the supply chain. This article is a case study of supply chain management system of LG Siltron, a major Korean silicon wafer manufacturer. The SCM system entails special information structure fitting well typical high-variety/high-customization product, and also gives application possibilities to the R&D based high-technology product made to the individual customer order.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.419-419
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• 2016

High efficiency silicon solar cell requires the textured front surface to reduce reflectance and to improve the light trapping. In case of mono-crystalline silicon solar cell, wet etching with alkaline solution is widespread. However, the alkali texturing methods are ineffective in case of multi-crystalline silicon wafer due to grain boundary of random crystallographic orientation. The acid texturing method is generally used in multi-crystalline silicon wafer to reduce the surface reflectance. However the acid textured solar cell gives low short-circuit current due to high reflectivity while it improves the open-circuit voltage. To reduce the reflectivity of multi-crystalline silicon wafer, double texturing method with combination of acid and reactive ion etching is an attractive technical solution. In this paper, we have studied to optimize RIE experimental condition with change of RF power (100W, 150W, 200W, 250W, 300W). During experiment, the gas ratio of SF6 and O2 was fixed as 30:10.