• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.1
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• pp.38-46
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• 2012

In this paper, we propose a decision feedback equalizer based on LDPC(Low Density Parity Check) code for the fast processing and performance improvement in OFDM system. LDPC code has good error correcting capability and its performance approaches the Shannon capacity limit. However, it has longer parity check matrix and needs more iteration numbers. In our proposed system, MSE(Mean Square Error) of signal between decision device and decoder is fed back to equalizer. This proposed system can improve BER performance because it corrects estimated channel response more accurately. In addition, the proposed system can reduce complexity because it has a lower number of iterations than system without feedback at the same performance. Simulation results evaluate and show the performance of OFDM system with the CFO and phase noise in multipath channel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2465-2473
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems including WiMAX and WLAN. A new design of DFU based on sign-magnitude arithmetic instead of two's complement arithmetic is proposed, resulting in 18% reduction of gate count for 96 DFUs array used in mobile WiMAX LDPC decoder. A multi-mode LDPC decoder for mobile WiMAX standard is designed using the proposed DFU. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 50 MHz clock has 268,870 gates and 71,424 bits RAM, and it is verified by FPGA implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2637-2642
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• 2015

The low-density parity check(LDPC) code is being widely used due to its outperformed error-correction ability. The decoder of the quasi-cyclic LDPC(QC-LDPC) codes, a kind of LDPC codes, requires a multi-size cyclic shifter(MSCS) performing rotation of various sizes. The MSCS can be implemented with a Benes network, which requires a $3{\times}3$ switch if the number of data to be rotated is a multiple of 3. This paper proposes a control signal generation with lower complexity and a faster $3{\times}3$ switch. For the experiment, the proposed schemes are applied to the MSCS of an IEEE 802.16e WiMAX QC-LDPC code decoder. The result shows that the delay is reduced by about 8.7%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4C
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• pp.299-304
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• 2008

For perpendicular magnetic recording channels, it is hard to expect improving the performance by using the PRML or NPML. Hence, we exploit LDPC code to improve the performance. In this paper, we examine a single message-passing detector/decoder matched to the combination of a perpendicular magnetic recording channel detector and an LDPC code decoder. We examine the performance of channel iteration with joint LDPC code on perpendicular magnetic recording channel, and simplify the complexity of the message-passing detector algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.939-947
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• 2010

The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.17-21
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• 2017

Since holographic data storage has the advantage of high recording density and data transfer rate, it is a candidate for the next generation storage systems. However, Holographic data storage system is affected by interpage interference and two dimensional intersymbol interference. Also, burst error occurs by physical impact. In this paper, we propose an LDPC product code using modified log-likelihood ratio and extrinsic information to correct burst error and improve performance of holographic data storage. The performance of proposed LDPC product code is 0.5dB better than that of the conventional LDPC code.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.317-325
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• 2012

In this paper, we consider the encoding scheme of Low Density Parity Check codes. In particular, using the Jacket Pattern and circulant permutation matrices, we propose the simple encoding scheme of Richardson's lower triangular matrix. These encoding scheme can be extended to a flexible code rate. Based on the simple matrix process, also we can design low complex and simple encoders for the flexible code rates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5A
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• pp.402-406
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• 2005

A multiple input multiple output orthogonal frequency division multiplexing (MIMO-OFDM) system using low-density parity-check (LDPC) code and iterative decoding is presented. The iterative decoding is performed by combining the zero-forcing technique and LDPC decoding through the use of the 'turbo principle.' The proposed system is shown to be effective with high order modulation and outperforms the space frequency block code (SFBC) method with iterative decoding.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.219-228
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• 2010

In this paper, performance of RS (Reed-Solomon), turbo and LDPC (low density parity check) code in the binary symmetric erasure channel is investigated. When the average erasure length is reduced, the frequency of short erasures is increased. The RS code shows serious performance degradation in such an environment since decoding is carried out symbol-by-symbol. As the erasure length is increased, however, the RS code shows much improved en-or performance. On the other hand, the message and corresponding parity symbols of the turbo code can be erased at the same time for the long erasures. Accordingly, iterative decoding of the turbo code can not improve error performance any more for such a long erasure. The LDPC code shows little difference in error performance with respect to the variation of the average erasure length due to the virtual interleaving effect. As a result, the LDPC code has much better erasure decoding performance than the RS and turbo code.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.22-30
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• 2011

In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys' Design Compiler using Chartered $0.18{\mu}m$ CMOS cell library. The synthesized design has the gate size of 455K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.