• 한국통신학회논문지
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• 제29권11C호
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• pp.1581-1591
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• 2004

본 논문에서는 주파수 옵셋 및 반송파 위상을 간단히 동시에 추정하기 위한 세 가지 알고리듬(low-complexity joint estimation algorithms : LJEAs)을 제안한다. 제안된 LJEA들의 핵심은 수신 신호의 주파수 및 위상 스펙트럼에서 주엽(main lobe)의 상관값을 이용하여 내분점을 기초로 보간한 후 주파수 옵셋 및 반송파 위상을 추정하되 주파수 옵셋을 먼저 추정하고 추정된 주파수 옵셋을 이용하여 반송파 위상을 동시에 추정하는 것이다. 제안된 LJEA들은 추정 범위( f$_{d}$${\times}$T$_{s}$ )가 1/2N$_{s}$ 혹은 1/N$_{s}$ 보다 작으며 이는 기존 알고리듬의 추정 범위와 비슷하다. 그러나 LJEA들은 오직 2N$_{s}$ 또는 4N$_{s}$ 의 복소 곱셈만이 필요하므로 기존 알고리듬에 비해서 매우 간단하다. 그럼에도 불구하고 LfEA들의 추정 성능은 기존 알고리듬의 성능보다도 우수함을 알 수 있다. 제안된 LJEA들은 위성 통신 시스템과 같은 버스트 모드 디지털 전송을 하는 시스템에서 주파수 옵셋 및 반송파 위상을 동시에 추정하기 위해 사용될 수 있다.

• 유통과학연구
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• 제13권4호
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• pp.55-64
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• 2015

Purpose - Multi-dimensional prices comprise multiple components such as monthly payments and a number of payments rather than a single lump-sum amount. According to previous studies, an increase in the number of price dimensions leads to a massive amount of cognitive stress resulting in incorrect calculation, and deterioration in the consistency of the price judgment. However, an increase only in the level of complexity of calculating multi-dimensional prices does not always result in a corresponding decrease in the accuracy of price evaluation. Since diverse variables could affect consumers' purchase-decision-making process, the results of price evaluation would be different. In this study, an empirical analysis was performed to determine how the accuracy of price evaluation varies depending on the extent of the complexity of price dimensions using product involvement and brand preference as moderating variables. Research design, data, and methodology - A survey was conducted on 260 students, and 252 effective responses were used for analysis. The data was analyzed using t-test, one-way ANOVA, and two-way ANOVA. In this study, six hypotheses were developed to examine the effect of product involvement and brand preference on consumers' evaluation effort of multi-dimensional prices. Results - As the number of price dimensions increased, accuracy of price evaluation appeared to be low in high involvement, as expected. However, it showed no differences in price evaluation effort when the level of complexity of calculating multi-dimensional prices is low. When a small number of price dimensions are presented in both cases of high and low involvement, accuracy of price evaluation is much higher in a weak brand preference. On the contrary, a strong brand preference enhances an accuracy of price evaluation only in case of low involvement when the number of price dimensions is increased. An interaction effect of product involvement and brand preference on consumers' evaluation of multi-dimensional prices did not exist irrespective of the level of complexity of calculating prices being high or low. Conclusions - When the number of price dimensions is small, consumers' effort for price evaluation shows almost no difference without the moderating effect of involvement, and a weak brand preference leads to a higher accuracy of price evaluation in an effort to make the best selection. No interaction effect of product involvement and brand preference was found except for a main effect of brand preference. When a price is composed of multiple dimensions rendering it more difficult to calculate the final price, the effort for price evaluation was expected to decrease only slightly in case of combination of high involvement and strong brand preference. This is because people have a higher purchase intentions and trust for that particular brand. However, the accuracy of price evaluation was much lower in cases of high involvement, and there was no interaction effect between product involvement and brand preference except for a main effect of involvement and brand preference, respectively.

• 한국통신학회논문지
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• 제30권2A호
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• pp.20-25
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• 2005

본 논문에서는 trace-back 동작 없이 디코딩이 가능한 변형된 레지스터 교환 (MRE) 방식을 블록 디코딩에 적용하여 전송 속도를 높이고 latency를 줄이는 비터비 디코딩 방식을 제안하였다. 변형된 레지스터 교환 방식을 블록 디코딩에 적용함으로써 디코딩 블록의 시작 상태를 결정하기 위해 필요한 동작 사이클을 줄여, 블록 디코딩을 사용하는 기존의 비터비 디코더보다 더 적은 latency를 가지게 되었다. 뿐만 아니라, 메모리를 더 효율적으로 사용할 수 있으면서 하드웨어의 구현에 있어서도 복잡도가 더 감소하게 된다. 또한 시작 상태를 결정하기 위해 필요한 trace-back 동작을 없애고 메모리를 줄여 이에 따른 전력 소모를 줄이는 저전력 동작이 가능하다. 제안된 방식은 같은 하드웨어 복잡도로도 메모리의 감소 또는 latency의 감소에 중점을 둔 설계가 가능하다. 또한, 몇 가지 디자인 파라미터를 변경하여 합성 단계에서 하드웨어 복잡도와 전송 속도를 Dade-off 할 수 있도록 스케일러블한 구조로 설계하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.317-320
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• 2002

In this paper, we will present the design and implementation of the KASUMI crypto algorithm and confidentiality algorithm (f8) to an hardware chip for 3GPP system. The f8 algorithm is based on the KASUMI which is a block cipher that produces a 64-bit output from a 64-bit input under the control of a 128-bit key. Various architectures (low hardware complexity version and high performance version) of the KASUMI are made with a Xilinx FPGA and the characteristics such as hardware complexity and thor performance are analyzed.

• 전자공학회논문지S
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• 제35S권2호
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• pp.50-57
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• 1998

In this paper, we propoe a log N-stage ATM concentator. ATM concentrator is used in the ATM access network to concentrate the traffic offered at UNI, so that high utilization of the newtork rewources is achieved. The concetrator may be used as a construction block in the design of ATM switch. We define abasic element, named equalizer, and decribe its function and theory to construct an efficient concentrator using the element. In addition, a control scheme to enhance the concentrator to a superconcentrator is presented, which enables the concentration to start from an arbitrary output. This scheme makes it possible to construct an efficient ditributior or a barrel shifter which are often used in ATM switch and other application. The proposed concentrator has a low hardware complexity of O(N log N), thus it is economical to implement. Also, the time complexity of proposed concentrator for determining the rouging is O(N log N), which is faster than that of the existing ones.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 컴퓨터소사이어티 추계학술대회논문집
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• pp.27-30
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• 2003

The recent technology developments introduce new difficulties into the test process by the increased complexity of the chip. Most widely used method for testing high complexity and embedded systems is built-in self-test(BIST). In this paper, we describe 5-stage pipeline system as circuit under testing(CUT) and proposed a BIST scheme for the hazard detection unit of the pipeline system. The proposed BIST scheme can generate sequential instruction sets by pseudo-random pattern generator that can detect all hazard issues and compare the expected hazard signals with those of the pipelined system. Although BIST schemes require additional area in the system, it proves to provide a low-cost test solution and significantly reduce the test time.

• 전기학회논문지
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• 제56권11호
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• pp.2033-2035
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• 2007

This paper proposes a novel iterative LMS-based decision feedback equalizer for short burst transmission with relatively short training sequence. In the proposed equalizer, the longer concatenated training sequence can provide the more sufficient channel information and the reused original training sequence can provide the correct decision feedback information. In addition, the overall adaptive processing is performed using the low complexity LMS algorithm. The study shows the performance of the proposed method is enhanced with the number of iterations and, furthermore, better than that of the conventional LMS-based DFEs with the training sequence of longer or equal length. Computational complexity is increased linearly with the number of iterations.

• 대한인간공학회지
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• 제32권5호
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• pp.429-435
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• 2013

Objective: This study aims to analyze job satisfaction and accident prevention according to job rotation system types in a motor company. Background: The study of a motor company's job rotation system has come to attention with enhancing productivity, preventing musculoskeletal disorders, and improving quality. Method: In this study, a survey was conducted to show job satisfaction rates according to job rotation systems. Also an investigation was done regarding industrial accidents and previous workers who are receiving treatment for musculoskeletal disorder over the last five years. Results: The job rotation system in this study has been carried out by voluntary decision of workers. Out of the job rotation types, the medium rotation complexity type had high job satisfaction whereas in a high or low rotation complexity type, which many workers prefer, led to less number of accidents and days of sick leave. Application: The results of this study are expected to be a fundamental data to job design.

• ETRI Journal
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• 제44권1호
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• pp.105-116
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• 2022

In this study, a novel group-indexed orthogonal frequency division multiplexing index modulation (OFDM-IM) scheme is proposed to achieve a tradeoff between spectral efficiency (SE) and bit-error-rate (BER) performance. In the proposed scheme, the total subcarriers in a group are divided into subgroups, and additional bits are transmitted by subgroup indexing, unlike the conventional OFDM-IM scheme, which uses index bits to select active subcarriers. With the proposed scheme, the additional degree of freedom provided by the number of active subgroups selected provides a tradeoff between spectral efficiency and BER performance. Decoding is performed in steps to reduce computional complexity in the decoder design. Simulaton results show that the number of active subgroups selected influences the proposed scheme's performance in terms of energy efficiency, spectral efficiency, and BER performance.

• ETRI Journal
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• 제27권5호
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• pp.557-562
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• 2005

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.