ETRI Journal

  • 제27권5호
  • /
  • Pages.557-562
  • /
  • 2005
  • /
  • 1225-6463(pISSN)
  • /
  • 2233-7326(eISSN)
한국전자통신연구원 (Electronics and Telecommunications Research Institute)
권호 표지

Design of Encoder and Decoder for LDPC Codes Using Hybrid H-Matrix

  • Lee, Chan-Ho (School of Electronic Engineering, Soongsil University)
  • 투고 : 2005.01.13
  • 발행 : 2005.10.31
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.

키워드

참고문헌

  1. Emerging Technologies Symposium: Broadband, Wireless Internet Access, 2000 IEEE Global Standardization of IMT-2000 O'Brien, F.E.;Guenther, R.D. Jr.
  2. ETRI J. v.25 no.5 Soft IP Compiler for a Reed-Solomon Decoder Park, Jong-Kang;Kim, Jong-Tae
  3. ETRI J. v.25 no.1 Trellis-Based Decoding of High-Dimensional Block Turbo Codes Kim, Soo-Young;Yang, Woo-Seok;Lee, Ho-Jin
  4. ETRI J. v.26 no.5 Independent Turbo Coding and Common Interleaving Method among Transmitter Branches Achieving Peak Throughput of 1 Gbps in OFCDM MIMO Multiplexing Junichiro Kawamoto;Takahiro Asai;Kenichi Higuchi;Mamoru Sawahashi
  5. ETRI J. v.26 no.1 A Viterbi Decoder with Efficient Memory Management Lee, Chan-Ho
  6. IRE Trans. Inform. Theory v.IT-8 Low Density Parity Check Codes Gallager, R.G.
  7. Electron. Lett. v.32 Near Shannon Limit Performance of Low Density Parity Check Codes MacKay, D.J.C.;Neal, R.M.
  8. IEEE Commun. Lett. v.5 On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit Chung, S.Y.;Forney, G.D.;Richardson, T.J. Jr.;Urbanke, R.
  9. Proc. of 2001 IEEE Int. Symp. on Circuits and Systems(ISCAS) v.4 On Finite Precision Implementation of Low-Density Parity-Check Codes Decoder Zhang, T.;Wang, Z.;Parhi, K.K.
  10. DVB-S2 DRAFT ETSI EN 302 307 V1.1.1 (204-06), Digital Video Broadcasting-Satellite Version 2
  11. IEEE Trans. Inform. Theory v.47 no.2 Efficient Encoding of Low-Density Parity-Check Codes Richardson, T,J,;Urbanke, R.
  12. IEE Electronics Lett. v.35 Low Density Parity Check Codes with Semi-Random Parity Check Matrix Ping, L.;Leung, W.K.;Phamdo, N.
  13. Signal Proc. Systems, 2002. IEEE Workshop (SiPS) A 54 Mbps (3,6)-Regular FPGA LDPC Decoder Zhang, T.;Parhi, K.K.
  14. IEEE Trans. Inform. Theory v.45 Good Error-Correcting Codes Based on very Sparse Matrices MacKay, D.J.C.
  15. IEEE Vehicular Technology Conf. Design of VLSI Implementation-Oriented LDPC Codes Zhong, H.;Zhang, T.
  16. Electronics Letters v.39 no.2 Analysis of Scaling Soft Information on Low Density Parity Check Codes Hao, J.
  17. IEEE Global Telecom. Conf. v.2 The $\pi$-Rotation Low-Density Parity Check Codes Echard, R.;Chang, S.C.
  18. IEEE Workshop, Signal Processing Systems (SiPS) VLSI Implementation-Oriented (3,k)-Regular Low-Density Parity Check Codes Zhang, T.;Parhi, K.K.
  19. IEEE Global Telecom. Conf., 2001 Extended Bit-Filing and LDPC Code Design Campelo, J.;Modha, D.S.
  20. Efficient VLSI Architectures for Error-Correcting Coding Zhang, T.
  21. IEEE Trans. Commun. v.50 no.3 Near Optimum Universal Belief Propagation Based Decoding of Low-Density Parity Check Codes Chen, J.;Fossorier, M.P.C.