• Proceedings of the KIEE Conference
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• 대한전기학회 2003년도 하계학술대회 논문집 D
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• pp.2705-2707
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• 2003

Over the past several years, the application extent of the real-time systems is being expanded with the progress of civilization. An effort to minimize power consumption at the system is being accomplished in several fields from the design of an analog/digital circuit up to the device level. Things of this effort have included the power optimum-technique to minimize power consumption at the digital logic circuit and the dynamic managed skill by means of the decision of the operating system. In this paper, we designed of low power system by using power-optimized method. As an effective low-power design, we designed the low power system which it has a monitoring system within the main board and a personal computer.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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• pp.31-34
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• 2004

In wireless communication systems, low-power metrics is becoming a burdensome problem in the portable terminal design, because of portability constraints. This paper presents design architecture of a low-power partial correlation Digital Matched Filter for the IMT-2000 communication systems. The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. The proposed architecture was verified by using Xilinx FPGA.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제4권1호
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• pp.79-83
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• 2004

This paper presents the performance analysis for CPL based design of a Low power digital neuroprocessor. We have verified the functionality of the components at the high level using Verilog and carried out the simulations in Silos. The components of the proposed digital neuroprocessor have also been verified at the layout level in LASI. The layouts have then been simulated and analyzed in Winspice for their timing characteristics. The result shows that the proposed digital neuroprocessor consistently consumes less power than other designs of the same function. It can also be seen that the proposed functions have lesser propagation delay and thus higher speed compared to the other designs.

• The Journal of the Korea Contents Association
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• 제7권2호
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• pp.92-99
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• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• The Transactions of the Korean Institute of Electrical Engineers P
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• 제58권4호
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• pp.432-436
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• 2009

This paper is described that advanced study on network design of remote diagnosis system for power facilities of electric railway. In the field, it is very difficult for worker to diagnosis power facilities including catenary because workers should be maintenance on AC power supply. Therefore, to properly design on remote diagnosis system, we have searched the inside and outside of the country-related technology trends. Also we confirmed that required technologies to design interface technology required for the development of sensor devices and the USN network was designed in accordance with required skills. Throughout variety of requirements, we have development iRFS based ZA sensors and iRFM to receive data of sensor. Also CC2420 is applied as single-chip which used 2.4GHz IEEE802.15.4 compliant RF tranciver designed for low-power and low-voltage wireless applications for ZigBee communication.

• Journal of the Korean Institute of Telematics and Electronics C
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• 제35C권2호
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• pp.36-47
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• 1998

Low power circuit techniques have been developed to realize the highest possible performance of embedded SRAM at 1V power supply with$0.5\mu\textrm{m}$ single threshold CMOS technology in which the unbalance between NMOS and PMOS threshold voltages is utilized to optimize the low power CMOS IC design. To achieve the best trade-off between the transistor drivability and the subthreshold current increase, the ground potential of memory array is raised to suppressthe subthreshold current. The problems of lower cellstability and bit-line dealy increase due to the enhanced array ground potential are evaluated to be controlled within the allowable range by careful circuit design. 160MHz, 128kb embedded SRAM with 3.4ns access time is demonstrated with the power consumption of 14.8mW in active $21.4{mu}W$ in standby mode at 1V power supply.

• Journal of Electrical Engineering and Technology
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• 제8권3호
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• pp.581-587
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• 2013

Among different linear motors, single-sided linear induction motors have been widely used in industry due to their simplicity and low construction cost. However, these types of motors suffer from low efficiency and power factor. In this paper, an effective procedure is proposed to design single-sided linear induction motors. The designed motor is simulated in MATLAB software in order to investigate the effect of design parameters on the performance of the machine. Regarding the obtained results, the Genetic Algorithm is employed to optimize the design considering product of efficiency and power factor as objective function. The results show significant improvement of the performance. Finally, experimental results and 2D finite element method is used to validate the model parameters and the optimization results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국해양정보통신학회 2009년도 춘계학술대회
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• pp.671-674
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• 2009

We design a low-power and low-area asynchronous EEPROM of 256 bits used in a passive UHF RFID tag chip. For a low-power solution, we use a supply voltage of 1.8V and design a Dickson charge pump using N-type Schottky diodes with a low-voltage characteristic. And we use an asynchronous interface and a separate I/O method for a low-area solution of the peripheral circuit of the designed EEPROM. And we design a Dickson charge pump using N-type Schottky diodes to reduce an area of DC-DC converter. The layout area of the designed EEPROM of 256 bits with an array of 16 rows and 16 columns using $0.18{\mu}m$ EEPROM process is $311.66{\times}490.59{\mu}m^2$.

• Nuclear Engineering and Technology
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• 제54권10호
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• pp.3745-3765
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• 2022

The concrete structures related to nuclear safety are threatened by accidental impact loadings, mainly including the low-velocity drop-weight impact (e.g., spent fuel cask and assembly, etc. with the velocity less than 20 m/s) and high-speed projectile impact (e.g., steel pipe, valve, turbine bucket, etc. with the velocity higher than 20 m/s), while the existing studies are still limited in the impact resistant design of nuclear power plant (NPP), especially the primary RC slab. This paper aims to propose the numerical simulation and theoretical approaches to assist the impact-resistant design of RC slab in NPP. Firstly, the continuous surface cap (CSC) model parameters for concrete with the compressive strength of 20-70 MPa are fully calibrated and verified, and the refined numerical simulation approach is proposed. Secondly, the two-degree freedom (TDOF) model with considering the mutual effect of flexural and shear resistance of RC slab are developed. Furthermore, based on the low-velocity drop hammer tests and high-speed soft/hard projectile impact tests on RC slabs, the adopted numerical simulation and TDOF model approaches are fully validated by the flexural and punching shear damage, deflection, and impact force time-histories of RC slabs. Finally, as for the two low-velocity impact scenarios, the design procedure of RC slab based on TDOF model is validated and recommended. Meanwhile, as for the four actual high-speed impact scenarios, the impact-resistant design specification in Chinese code NB/T 20012-2019 is evaluated, the over conservation of which is found, and the proposed numerical approach is recommended. The present work could beneficially guide the impact-resistant design and safety assessment of NPPs against the accidental impact loadings.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제58권1호
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• pp.199-202
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• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.