• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1019-1022
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• 2003

This paper has proposed a 4- bit 20MHz Flash A/D converter design available analog signal processing and realized its intergrated circuit. The parallel comparison method A/D converter quantized analog signals swiftly using various converters. Also this theme has designed economic power dissipation circuit using a preamplifier of low volt & power CMOS comparator. Also the system was fabricated by Hynix 0.35um CMOS process.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.434-438
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• 2000

In this paper the low cost sensorless control circuit for a PM synchronous motor without the mechanical rotor position sensors is presented. The sensorless control algorithm and position detection circuit for the sinusoidal current wave drive is more complex than that of the rectangular current wave drive. The proposed position sensing circuit is composed of an operational amplifier and several passive elements. The design procedures for getting the optimal parameters for the position sensing circuit are presented. The performance of the proposed algorithm is verified through the simulations and experiments.

• Journal of IKEEE
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• v.25 no.2
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• pp.309-314
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• 2021

The proposed preamplifier for the static random access memory reduces the time required for the sense amplifier enable during the read operation by 55%, which leads to a significant speed up the total spped. This is attirbuted to the novel circuit techqniue that cancels out the transistor mismatch which is induced by the process variation. In addition, a selective enable circuit for preamplifier circuit is proposed, so the proposed preamplifier is enabled only when it is required. Accordingly the energy overhead is limited below 4.45%.

• Journal of IKEEE
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• v.22 no.1
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• pp.174-179
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• 2018

In this paper, design of high-efficiency DC-DC converter is presented for low-power PMIC (power management integrated circuit). As PMIC technologies for IoT and wearable devices have been continuously improved, high-efficiency energy harvesting schemes should be essential. Since the supply voltage resulting from energy harvesting is low and widely variable, design techniques to achieve high efficiency over a wide input voltage range are required. To obtain a constant switching frequency for wide input voltage range, frequency compensation circuit using supply-voltage variation sensing circuit is included. In order to obtain high efficiency performance at very low-power condition, accurate burst-mode control circuit was adopted to control switching operations. In the proposed DC-DC buck converter, output voltage is set to be 0.9V at the input voltage of 0.95~3.3V and maximum measured efficiency is up to 78% for the load current of 180uA.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.6
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• pp.9-17
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• 2011

The high-power LED (Light Emitting Diode) which is recently gaining popularity as a digital light source has such advantages as low power consumption, long life, fast switching speed, and high efficiency. Thus, many efforts are being made to use the high-power LEDs for general lighting. This paper proposes LED driving circuit uses a DC/DC converter that can recover energy to compensate for the current variations caused by changes in LED equivalent resistance following a temperature change instead of serial resistance. The maximum input voltage of this DC/DC converter has low voltage variations by temperature change when the rated current is formed. In order to return current to the input side, we need a high boosting at low power. Thus, to improve the low efficiency of power converter, the power converter can be configured in such a way to gather the powers of low-capacity DC/DC converters and return the total power. Experiments showed that the proposed system improved efficiency compared to the conventional LED drive using the existing DC/DC converter.

• Journal of the Korea Institute of Military Science and Technology
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• v.10 no.2
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• pp.152-159
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• 2007

This paper describes the design, fabrication, and measurement of ROIC(ReadOut Integrated Circuit) for $320{\times}256$ IRFPA(InfraRed Focal Plane Array). A ROIC plays an important role that transfer photocurrent generated in a detector device to thermal image system. Recently, the high performance and low power ROIC adding various functions is being required. According to this requirement, the design of ROIC focuses on 7MHz or more pixel rate, low power dissipation, anti-blooming, multi-channel output mode, image reversal, various windowing, and frame CDS(Correlated Double Sampling). The designed ROIC was fabricated using $0.6{\mu}m$ double-poly triple-metal Si CMOS process. ROIC function factors work normally, and the power dissipation of ROIC is 33mW and 90.5mW at 7.5MHz pixel rate in the 1-channel and 4-channel operation, respectively.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.2
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• pp.111-121
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• 1999

This paper deals with an active gate drive (AGD) technolo밍T for high power IGBTs. It is based on an optimal c combination of several requirements necessmy for good switching performance under hard switching conditions, The s scheme specifically combines together the slow drive requirements for low noise and switching stress and the fast driver requirements for high speed switching and low switching energy loss The gate drive can also effectively dampen oscillations during low cunent turnlongrightarrowon transient in the IGBT, This paper looks at the conflicting requirements of the c conventional gate dlive circuit design and the experimental results show that the proposed threelongleftarrowstage active gate dlive t technique can be an effective solution.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2705-2707
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• 2003

Over the past several years, the application extent of the real-time systems is being expanded with the progress of civilization. An effort to minimize power consumption at the system is being accomplished in several fields from the design of an analog/digital circuit up to the device level. Things of this effort have included the power optimum-technique to minimize power consumption at the digital logic circuit and the dynamic managed skill by means of the decision of the operating system. In this paper, we designed of low power system by using power-optimized method. As an effective low-power design, we designed the low power system which it has a monitoring system within the main board and a personal computer.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.731-734
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• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at the same time. Maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, we performed the layout high speed I/O interface circuit with the low triggered ESD protection device in one-chip.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.22-25
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• 2007

The paper describes a power factor correction high efficiency PWM single-phase rectifier. Its good characteristics such as simple circuit structure, simple PWM control, low switch stress, and low VAR rating of commutation circuits make the proposed rectifier very suitable for various unidirectional power applications. In particular, the design guide line is suggested to make the circuit design of the proposed rectifier easy and fast.