• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.916-917
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• 2008

In this paper, Switching damage of switches that is used to proposed power conversion system is reduced by soft switching way. dissipation by part resonance and my resonance stress for resonance of resonance circuit are decreased. Is acted by conversion system high effectiveness. Have following characteristic. Design snubber circuit that is used by switch protection in existent hard work rate Topology by resonant circuit for sogt switching, circuit structure was simple and control system is easy. Also, Can generate free output voltage by multi level Tuesday of output that use individuation Power Cell's Phase Shift PWM, and Low-end switching frequency the harmonic is few.

• Journal of Power Electronics
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• v.18 no.4
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• pp.965-974
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• 2018

A new zero-voltage-switching (ZVS) push-pull pulse-width modulation (PWM) converter is proposed in this paper. The wide ZVS condition for all of the switches is obtained by utilizing the energy stored in the output inductor and magnetizing inductance. As a result, the switching losses can be dramatically reduced. A simple auxiliary circuit including two small diodes and one capacitor is added at the secondary side of a high frequency (HF) transformer to reset the primary current during the circulating stage and to clamp the voltage spike across the rectifier diodes, which enables the use of low-voltage and low-cost diodes to reduce the conducting and reverse recovery losses. In addition, there are no active devices or resistors in the auxiliary circuit, which can be realized easily. A detailed steady operation analysis, characteristics, design considerations, experimental results and a loss breakdown are presented for the proposed converter. A 500 W prototype has been constructed to verify the effectiveness of the proposed concept.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.921-926
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• 2015

For the over-heat protection purpose in power strip devices, over-current detection/protection circuits, such as bimetal, switching circuit, and microprocessor-based relay circuit, have been widely setup in high-end products. Most of these circuits are connected to the power line in parallel and, thus, they are sensitive to the line voltage and current distortion. Moreover, these protection circuits are often costly and, therefore, it is hard to meet the commercial requirements. A low-cost over-current detection circuit with the contactless current transducer is designed and tested in this paper. The detection circuit is galvanically isolated from the power line and, thus, less sensitive to the line voltage distortion. The experimental results show that the proposed circuit accurately operates despite of its simple structure and low-cost electronic parts.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.533-536
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• 2016

This paper describes a vibrational energy harvesting circuit with MPPT control. A high-performance AC-DC converter of which the efficiency is improved by using body-bias technique and bulk-driven technique is proposed and applied for the vibrational energy harvesting circuit design. MPPT (Maximum Power Point Tracking) control function is implemented using the linear relationship between the open-circuit voltage of a vibrational device and its MPP voltage. The designed MPPT control circuit traces the maximum power point by periodically sampling the open circuit voltage of a vibrational device, makes the reference voltages using sampled voltage and delivers the maximum available power to load. The proposed circuit is designed with a $0.35{\mu}m$ CMOS process, and the chip area is $1.21mm{\times}0.98mm$.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.144-147
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• 2005

This paper is proposed an 8$\times$8 bit parallel multiplier for low power consumption. The 8$\times$8 bit parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing tile previous works, this circuit is reduced the power consumption rate of 8.2% and the power-delay-product of 11.1%. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.35$\{\mu}m$ standard CMOS process.

• ETRI Journal
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• v.45 no.4
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• pp.570-580
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• 2023

Sensor nodes are the most significant part of a wireless sensor network that offers a powerful combination of sensing, processing, and communication. One major challenge while designing a sensor node is power consumption, as sensor nodes are generally battery-operated. In this study, we proposed the design of a low-power, long range-based wireless sensor node with flexibility, a compact size, and energy efficiency. Furthermore, we improved power performance by adopting an efficient hardware design and proper component selection. The Nano Power Timer Integrated Circuit is used for power management, as it consumes nanoamps of current, resulting in improved battery life. The proposed design achieves an off-time current of 38.17309 nA, which is tiny compared with the design discussed in the existing literature. Battery life is estimated for spreading factors (SFs), ranging from SF7 to SF12. The achieved battery life is 2.54 years for SF12 and 3.94 years for SF7. We present the analysis of current consumption and battery life. Sensor data, received signal strength indicator, and signal-to-noise ratio are visualized using the ThingSpeak network.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.251-265
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• 2001

As the device scaling proceeds, the operating voltage(VDD) of giga-bit DRAMs is expected to be reduced to 1.5V or down, fir improving the device reliability and reducing the power dissipation. Therefore the low-voltage circuit design techniques are required to implement giga-bit DRAMs. In this work, state-of-art low-voltage DRAM circuit techniques are reviewed, and four kinds of low-voltage circuit design techniques are newly proposed for giga-bit DRAMs. Measurement results of test chips and SPICE simulation results are presented for the newly proposed circuit design techniques, which include a hierarchical negative-voltage word-line driver with reduced subthreshold leakage current, a two-phase VBB(Back-Bias Voltage) generator, a two-phase VPP(Boosted Voltage) generator and a bandgap reference voltage generator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.2
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• pp.174-180
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• 2008

The pulsed amplifier which switches the main supply voltage of RF amplifier according to input pulse signal has good efficiency and low noise level between pulses. And it has simple structure because it doesn't need a pulse modulator at input port. The pulsed amplifier using the conventional switching circuit has slow fall time compared to rise time. We proposed the novel switching circuit for improving the fall time of pulsed amplifier The proposed switching circuit is implemented by replacing FET of conventional circuit with BJT. As a result of appling this circuit to RF pulsed amplifier, the rise and fall time are 5.7 ns and 21.9 ns at 27 dBm output power, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.12
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• pp.1602-1610
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• 2018

Induction heating can convert electrical energy to thermal energy with high conversion efficiency and quick heating. Currently, a current source rectifier/inverter-fed parallel resonant circuit is widely used as an induction heating power supply for forging applications. However, the conventional induction heating power supplies composed of phase-controlled rectifier and SCR inverter have low efficiency and low power factor at input side, and require additional starting circuitry. So this paper proposes new induction heating power supply topologies for forging applications which have high power factor, high efficiency, and large output power. It also suggests detailed design guideline.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.77-84
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• 2015

This paper presents the design of a low-power, low area 256-radix 16-bit crossbar switch employing a 2D Hyper-X network topology. The Hyper-X crossbar switch realizes the high radix of 256 by hierarchically combining a set of 4-radix sub-switches and applies three modifications to the basic Hyper-X topology in order to mitigate the adverse scaling of power consumption and propagation delay with the increasing radix. For instance, by restricting the directions in which signals can be routed, by restricting the ports to which signals can be connected, and by replacing the column-wise routes with diagonal routes, the fanout of each circuit node can be substantially reduced from 256 to 4~8. The proposed 256-radix, 16-bit crossbar switch is designed in a 65 nm CMOS and occupies the total area of $0.93{\times}1.25mm^2$. The simulated worst-case delay and power dissipation are 641 ps and 13.01 W when operating at a 1.2 V supply and 1 GHz frequency. In comparison with the state-of-the-art designs, the proposed crossbar switch design achieves the best energy-delay efficiency of $2.203cycle/ns{\cdot}fJ{\cdot}{\lambda}2$.