• Journal of the Korean Society for Heat Treatment
• /
• v.17 no.2
• /
• pp.78-86
• /
• 2004

Effects of the annealing parameters on the formation of ferrites transformed at low temperatures were studied in cold-rolled ultra low carbon steels with niobium and/or chromium. Niobium and chromium were found to be effective in the formation of the low temperature transformation ferrites. The low temperature transformation ferrites more easily formed when both higher annealing temperature and longer annealing time, allowing substitutional alloying elements to distribute between phases, are in combination with faster cooling rate. It was found from EBSD study that the additions of niobium or chromium resulted in the increase in the numbers of high angle grain boundaries and the decrease in those of the low angle grain boundaries in the microstructures. Both granular bainitic ferrite and bainitic ferrite were characterized by the not clearly etched grain boundaries in light microscopy because of the low angle grain boundaries.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.11a
• /
• pp.224-225
• /
• 2007

The Low dielectric properties of epoxy/Annealing $SiO_2$ composites using Annealing new material of nanosized amorphous particles were investigated as function frequency, temperature and filler contents composition. The dielectric constant decrease with increasing frequency and also increase with increasing ambient temperature. The dielectric constant decrease with increase annealing filler contents for epoxy base. The result of x-ray diffraction could obtained single crystal of annealing $SiO_2$ from 500nm amorphous $SiO_2$ powder.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.37 no.1
• /
• pp.43-47
• /
• 2024

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using high-temperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), and off-state current (I_OFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

• Tribology and Lubricants
• /
• v.37 no.2
• /
• pp.62-70
• /
• 2021

The problem with intermetallics coating using the heat of molten casting is that the heat generated during combustion synthesis dissolves the coating and the substrate metal. This study investigates whether pre-annealing before synthesis can control the reaction heat, with the aim of Ni₃Al coating on the casting surface. Therefore, the effects of the annealing temperature and time on the combustion synthesis behavior of the powder compact of Ni-25at%Al after annealing were investigated. As results, the reaction heat when synthesized decreased as the annealing temperature was high and the annealing time was longer. This was attributed to the fact that Al was diffused to Ni particles during low temperature annealing and intermediate Ni-Al compounds were formed during high temperature annealing. After combustion synthesis, however, it was found that their microstructures were almost identical except for the amount of intermediate intermetallics. Furthermore, an annealing temperature above 450℃, at which intermediate compounds begin to form, is needed to prevent the dissolving problem during synthesizing. The intermetallics synthesized after annealing at higher temperature and prolonger annealing time showed a good wear resistance. This might be because much intermediate intermetallics of high hardness were remained in the microstructure.

• Journal of the Korean Ceramic Society
• /
• v.52 no.4
• /
• pp.279-283
• /
• 2015

Ni (100 nm thick) was deposited onto synthesized diamonds to fabricate etched diamonds. Next, those diamonds were annealed at varying temperatures ($400{\sim}1200^{\circ}C$) for 30 minutes and then immersed in 30 wt% $HNO_3$ to remove the Ni layers. The etched properties of the diamonds were examined with FE-SEM, micro-Raman, and VSM. The FE-SEM results showed that the Ni agglomerated at a low annealing temperature (${\sim}400^{\circ}C$), and self-aligned hemisphere dots formed at an annealing temperature of $800^{\circ}C$. Those dots became smaller with a bimodal distribution as the annealing temperature increased. After stripping the Ni layers, etch pits and trigons formed with annealing temperatures above $400^{\circ}C$ on the surface of the diamonds. However, surface graphite layers existed above $1000^{\circ}C$. The B-H loop results showed that the coercivity of the samples increased to 320 Oe (from 37 Oe) when the annealing temperature increased to $600^{\circ}C$ and then, decreased to 150 Oe with elevated annealing temperatures. This result indicates that the coercivity was affected by magnetic domain pinning at temperatures below $600^{\circ}C$ and single domain behavior at elevated temperatures above $800^{\circ}C$ consistent with the microstructure results. Thus, the results of this study show that the surface of diamonds can be etched.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.24 no.7
• /
• pp.525-531
• /
• 2011

In this paper, experimental analyses have been performed to compare the electrical characteristics of n channel LT(low temperature) and HT(high temperature) poly-Si TFTs(polycrystalline silicon thin film transistors) on quartz substrate according to activated step annealing. The size of the particles step annealed at low temperature are bigger than high temperature poly-Si TFTs and measurements show that the electric characteristics those are transconductance, threshold voltage, electric effective mobility, on and off current of step annealed at LT poly-Si TFTs are high more than HT poly-Si TFT's. Especially we can estimated the defect in the activated grade poly crystalline silicon and the grain boundary of LT poly-Si TFT have more high than HT poly-Si TFT's due to high off electric current. Even though the size of particles of step annealed at low temperature, the electrical characteristics of LT poly-Si TFTs were investigated deterioration phenomena that is decrease on/off current ratio depend on high off current due to defects in active silicon layer.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.274-277
• /
• 2000

Thin Film Transistor(TFTs) were fabricated from poly-Si crystallized by a two-step annealing process on glass substrates. The combination of low-temperature(500$^{\circ}C$) Metal-Induced Lateral Crystallization(MILC) furnace annealing and high -temperature (700$^{\circ}C$) rapid thermal annealing leads to the improvement of the material quality The TFTs measured with this two-step annealing material exhibit better characteristics than those obtained by using conventional MILC furnace annealing.

• Journal of the Korean Society for Precision Engineering
• /
• v.11 no.2
• /
• pp.173-181
• /
• 1994

A Cold spot temperature control system for the batch annealing furnace has been estabilished in order to reduce energy consumption to improve productivity and stabilize the propertics of products. Therefore we confirmed a relation between annealing cycle time and atmospheric gas, variation of coil cold spot temperature with time during heating and actual temperature measurements at mid-width of each coil during heating and actual temperature measurements at mid-width of each coil during soaking. The results of the tempaeature variation effect on the batch annealing are as follows. 1) Heating time is reduced to one half with increasing atmospheric gas flow rate and changing of atmospheric gas component from HNx to Ax gas, and annealing cycle time is reduced to 2.7 times. 2) In case of short time healing, the slowest heating part is the center of B coil, in case of long time heating, the low temperature point moves from the center of coil to inside coil. And the temperature in this part is higher than other parts when cooling. When finished heating, the cold spot is located 1/3 of coil inside in case of HNx atmospheric gas. But center of coil in case of Ax atmospheric gas. 3) The outside of top coil is the highest temperature point when heating, which becomes the lowest temperature point when cooling. So, this point becomes high temperature zone at heating and low temperature zone at cooling, It has relation according to atmospheric gas component and flow rate. 4) Soaking time at batch annealing cycle determination is made a decision by the input coil width, and soaking time for quality homogenization of 1214mm width coil must be 2.5 hours longer than that of 914mm width coil for the same ciol weight. 5) Annealing cycle time with Ax atmospheric gas is extended 1 hour in of slow cooling during 5 hours in order to avoid rapid cooling.

• Journal of the Korean institute of surface engineering
• /
• v.27 no.4
• /
• pp.234-240
• /
• 1994

A large area impurity doping method for poly-Si TFT LCD has been developed. The advantage of this method is the doping of impurities into Si over a large area without mass separation and beam scanning. Phosphorus diluted in hydrogen was discharged by RF(13.56MHz) power and ions from discharged gas were accelerated by DC acceleration voltage and were implanted into deposited Si films. The annealing characteristic of this method was similar to that of the ion implantation method in the low doping concentration. Three mechanisms were evolved in the annealing characteristics of phosphorus doped Si films. Point defects annihilation and the retrogradation of dopant atoms at grain boundaries as a result of grain growth played a major role at low and high annealing temperature, respectively. However, due to the dopant segregation, the reverse annealing range existed at intermediate annealing temperature.

• Journal of the Korean Ceramic Society
• /
• v.43 no.9 s.292
• /
• pp.527-531
• /
• 2006

In order to study the influence of post-annealing treatment on the frequency characteristics of the Li doped ZnO(Li:ZnO) FBAR(Film Bulk Acoustic Resonator) device, we investigated the material and electrical properties of Li:ZnO films in the annealing temperature range from 300 to $500^{\circ}C$. In our samples, as annealing temperature was increased, Li:ZnO films showed the improvement of high c-axis orientation and resistance value with relieved stress and low surface roughness. In addition to, the return loss in the frequency property of fabricated FBAR was improved by annealing treatment from 24.9 to 29.8dB. From experimental results, the optimum post-annealing temperature for FBAR is $500^{\circ}C$ and it can obtain excellent Li:ZnO FBAR performance with stronger c-axis orientation, smoother surface, relieved stress, and lower loss factor.