• 한국ITS학회:학술대회논문집
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• 2010.05a
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• pp.92-95
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• 2010

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1085-1088
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• 1998

In this paper, we propose a hardware reduced multiplier for DSP applications. In many DSP application, all of multiplier products were not used, but only upper bits of rpoduct were used. Kidambi proposed truncated unsigned multiplier for this idea. In this paper, we abopt this scheme to Booth multiplier which can be used for real DSP systems. Also, zero input guarantees zero output that was not provided in the previous work.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.4
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• pp.262-266
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• 2011

In high data-rate communication systems, encryption/decryption must be processed in high speed. In this paper, we implement CCM security mode which is the basis of security. Specifically, we combine CCM with AES block encryption algorithm in hardware. With the combination, we can carry out encryption/decryption as well as data transmission/reception simultaneously without reducing data-rate, and we keep low-power consumption with high speed by optimizing CCM block.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.317-320
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• 2000

This paper proposes a voltage compensation method to improve the control performance of B4 inverter which is studied for low-cost drive systems. The B4 inverter employs only four switches and it has a center-tapped connection in the split dc-link capacitors to one phase of a three-phase motor. In the B4 topology unbalan-cd three-phase voltages will be generated by the dc link voltage ripple. To solve this problem we present a voltage compensation method which adjusts switching times considering dc link voltage ripple. The proposed method is verified by simulation results,

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.1_2
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• pp.52-57
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• 2001

이 논문에서는 우리는 버스에서의 연속된 데이터 전송 시 발생하는 데이터 값의 천이를 줄이는 새로운 버스-인버트 코딩에 적용 된 것과는 달리, 우리의 기법은 다양한 버스 분할을 시도하여, 각 분할에 독립적으로 버스-인버트 코딩을 적용하여 전체의 데이터 값 천이를 최소화하고자 한다. 실제 회로를 통한 실험에서 기존의 버스-인버트 코딩과 비교하여 우리의 제안한 기법은 데이터 값의 천이를 전체적으로 10%-50% 수준으로 줄일 수 있음을 보여 준다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2007.11a
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• pp.55.1-55.1
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• 2007

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.1229-1232
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• 1996

This paper proposes the passive redundancy algorithm of multi-controller structure applicable to the steam generator level control system in the low power operating range. In the passive redundancy scheme of multi-controller structure, two suitable controllers exist if the plant is strongly stabilizable. One of the two controllers can be selected arbitrarily only if it is stable. In particular, this paper shows that the passive redundancy scheme can be efficiently used with PID and GPC control algorithms through simulation studies on the control of the steam generator.

• Journal of IKEEE
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• v.12 no.2
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• pp.81-86
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• 2008

In wireless communication system using 2.4GHz radio link, data rate varies with time due to interferences, which causes the performance degradation. Therefore, effective transmission methods are required to obtain better performance according to varying data rate. This paper proposes a novel method that increases the data rate, as well as the influence of different loop-filter bandwidths on the performance of the PLL. Experimental results show that the proposed method is effective because it can achieve higher throughput in various data rate.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.443-447
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• 1999

The AC drive systems of a voltage source inverter and an induction motor. The inverter non linearity caused by the turn on/off time dependency of the current level in the switching IGBT is described in the first part of this paper. To improve the low-speed drive characteristics, accurate applied voltage calculation is proposed under considerations of the compensations for the quantization error in the digital controller, the forward voltage drop of switching drives and the dead time of the inverter. The experimental studies show the improved drive characteristics.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.131.1-131
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• 2001

At the present time, multimedia chip, internet application, and network equipment is designed by using ARM core. Because it has a good debugging, software compiler and needed low power. We must process a data coding to send a multimedia data by real time. So need to connect software and hardware algorithm. In this research, We design interface for ARM9/AMBA based board using VHDL for these function implementation. The board is used the ARM company´s ARM940T for software function implementation and Xilinx company´s Virtex E2000 for hardware function algorithm. The various hardware algorithm (ME,ME,DCT) block for performance can be implemented on this system.