A Hardware Reduced Multiplier for Low Power Design

저전력 설계를 위한 면적 절약형 곱셈기 구조에 관한 연구

In this paper, we propose a hardware reduced multiplier for DSP applications. In many DSP application, all of multiplier products were not used, but only upper bits of rpoduct were used. Kidambi proposed truncated unsigned multiplier for this idea. In this paper, we abopt this scheme to Booth multiplier which can be used for real DSP systems. Also, zero input guarantees zero output that was not provided in the previous work.