• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.326-332
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• 2017

A switched VCO-based UWB transmitter for 3-5 GHz is implemented using $0.18{\mu}m$ CMOS technology. Using RF switch and timing control of DPGs, the uniform RF power and low power consumption are possible regardless of carrier frequency. And gate control of RF switch enables the undesired side lobe rejection sufficiently. The measured pulse width is tunable from 0.5 to 2 ns. The measured energy efficiency per pulse is 4.08% and the power consumption is 0.6 mW at 10 Mbps without the buffer amplifier.

• Journal of Power Electronics
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• v.10 no.5
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• pp.461-467
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• 2010

This paper proposes a new soft-switched Sepic converter. It has low switching losses and low conduction losses due to its auxiliary communicated circuit and synchronous rectifier operation, respectively. Because of its positive and buck/boost-like DC voltage transfer function (M=D/(1-D)), the proposed converter is desirable for use in distributed power systems. The proposed converter has versions both with and without a transformer. The paper also suggests some design guidelines in terms of the power circuit and the control loop for the proposed converter.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.2
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• pp.201-206
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• 2007

In this paper, we propose the efficient low power test methodology of NoC(Network-on chip) for the test of core-based systems that use this platform. To reduce the power consumption of transferring data through router channel, the scan vectors are partitioned into flits by channel width. The don't cares in unspecified scan vectors are mapped to binary values to minimize the switching rate between flits. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method leads to about 35% reduction in test power.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.1-10
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• 2007

In recent few years, low-power electronics has been a leading drive for technology developments nourished by rapidly growing market share. Mobile DRAM, as a fundamental block of hand-held devices, is now becoming a product developed by limitless competition. To support application specific mobile features, various new power-reduction schemes have been proposed and adopted by standardization. Tightened power budget in battery-operated systems makes conventional schemes not acceptable and increases difficulty of the circuit design. The mobile DRAM has successfully moved down to 1.5V era, and now it is about to move to 1.2V. Further voltage scaling, however, presents critical problems which must be overcome. This paper reviews critical issues in mobile DRAM design and various circuit schemes to solve the problems. Focused on analog circuits, bitline sensing, IO line sensing, refresh-related schemes, DC bias generation, and schemes for higher data rate are covered.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.3
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• pp.1393-1405
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• 2017

It is well known that duty-cycling control by dynamically adjusting the polling interval according to the traffic loads can effectively achieve power saving in wireless sensor networks. Thus, there has been a significant research effort in developing polling interval adaptation schemes. Especially, Dynamic Low Power Listening (DLPL) scheme is one of the most widely adopted open-looping polling interval adaptation techniques in wireless sensor networks. In DLPL scheme, if consecutive idle (busy) samplings reach a given fixed threshold, the polling interval is increased (decreased). However, due to the trial-and-error based approach, it may significantly deteriorate the system performance depending on given threshold parameters. In this paper, we propose a novel DLPL scheme, called SDL (Sequential hypothesis testing based Dynamic LPL), which employs sequential hypothesis testing to decide whether to change the polling interval conforming to various traffic conditions. Simulation results show that SDL achieves substantial power saving over state-of-the-art DLPL schemes.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1525-1528
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• 2008

High-luminance CNT-FED character-displays using simple line-rib-structure was performed. One display-panel had $48{\times}480$-dots and the sub-pixel pitch was 1mm. Another panel had $32{\times}256$-color-pixels, and the subpixel size was $0.6mm{\times}1.8mm$. The power consumption was less than 10W at character-displaying module. It should be useful for public display even under emergent no-power condition.

• Journal of Communications and Networks
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• v.7 no.4
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• pp.462-470
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• 2005

We propose a multi-rate and multi-BEP transmission scheme using adaptive overlapping pulse-position modulator (OPPM) and optical power controller in optical code division multiple access (CDMA) networks. The proposed system achieves the multi-rate and multi-BEP transmission by accommodating users with different values of OPPM parameter and transmitted power in the same network. The proposed scheme has advantages that the system is not required to change the code length and number of weight depending on the required bit rate of a user and the difference of bit rates does not have so much effect on the bit error probabilities (BEPs). Moreover, the difference of transmitted powers does not cause the change of bit rate. We analyze the BEPs of the four multimedia service classes corresponding to the com­binations of high/low-rates and low/high-BEPs and show that the proposed scheme can easily achieve distinct differentiation of the service classes with the simple system configuration.

• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.7-9
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• 2001

Many developing countries has been voltage unstable and the inter- change capability in Korea is limited by voltage instability. In analyzing voltage stability, load model has been considered as constant power, but actual loads vary as voltage changes. In order to incorporating voltage-dependent load model. we need the low-side of P-V curve that can not be obtained by general load flow algorithm. This paper proposes a modified GCF algorithm to obtain a full low-side of P-V curve and a accurate voltage assessment index considering load model. 5-bus sample system and 19-bus real power system are applied to simulate the proposed GCF. Also. the effect of reactive power compensation is illustrated in same systems.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.321-324
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• 2001

This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32$\times$32 bit multiplication, and was designed using verilog HDL and 0.35${\mu}{\textrm}{m}$, 3V, 4M CMOS standard cell library. Its target operating speed is 40MHz, area lower than 10000 gate counts, and 10mW/MHz of power.

• Transactions of The Korea Fluid Power Systems Society
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• v.1 no.2
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• pp.15-19
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• 2004

In this study, Design and simulation for low power consumption type pneumatic on-off micro valve was performed. And flow characteristics of the micro valve by stroke change was numerically investigated. As a result, it is shown that magnetic force(6.8N) is exerted enough to move poppet with 0.438mm stroke with 0.01 seconds of response time, and that there is no magnetic force emitted by yoke. Under the condition of poppet stroke smaller than about 0.4mm, dynamic pressure acts to poppet wall up to supply pressure level. But, that is decreasing to 40% when poppet stroke is 0.8mm.