• Journal of electromagnetic engineering and science
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• v.4 no.4
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• pp.156-161
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• 2004

The MMIC cascode VCO is designed, fabricated, and measured for Ku-band Low Noise Blcok(LNB) system using InGaP/GaAs HBT technology. The phase noise of -116.4 dBc/Hz at 1 MHz offset with output power of 1.3 dBm is obtained at 11.526 GHz by applying 3 V and 11 mA, which is comparatively better characteristics than compared with the different configuration VCOs fabricated with other technologies. The simulated results of oscillation frequency and second harmonic suppression agree with the measured results. The phase noise is improved due to the use of the smallest value of inductor in frequency determining network and the InGaP ledge function of the technology. The chip size of $830\time781\;{\mu}m^2$ is also achieved.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.465-468
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• 2004

In this paper, we describe the design and implementation of the new current-current negative feedback (CCNF) voltage-controlled oscillator (VCO), which suppresses 1/f induced low-frequency noise. By means of the CCNF, the high-frequency noise as well as the low-frequency noise is prevented from being converted into phase noise. The proposed CCNF VCO shows 11-dB reduction in phase noise at 10 kHz offset, compared with the conventional differential VCO. The phase noise of the proposed VCO is -87 dBc/Hz at 10 kHz offset frequency from 5.5-GHz carrier. The proposed VCO consumes 14.0 mA at 2.0 V supply voltage, and shows single-ended output power of -12.0 dBm.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.39-49
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• 1999

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.6 no.1 s.12
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• pp.38-46
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• 2007

In this paper an X-band low phase noise HBT oscillator using a planar type MMIC resonator is designed. The chip area of the proposed resonator shows a quarter of the conventional hair-pin resonator using distributed transmission lines. The measurement results show oscillation frequency of 8.295 GHz, the power output of 4.8 dBm, and phase noise characteristic of -106.8 dBc/Hz and -121.7 dBc/Hz at 100 kHz and 1 MHz offset frequencies respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.42-47
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• 2017

This paper proposes a new series-coupled voltage-controlled oscillator (VCO). The proposed VCO consists of four current-reuse Armstrong VCOs (CRA-VCOs) coupled by four transformers. The series-coupling, current-reuse, and Armstrong topologies improve the phase noise performance by increasing the negative-Gm of the VCO core with half the current consumption of a conventional differential VCO. The proposed VCO consumes 6.54 mW at 9.78 GHz from a 1-V supply voltage. The measured phase noise is -115.1 dBc/Hz at an offset frequency of 1 MHz, and the FoM is -186.5 dBc/Hz. The frequency tuning range is from 9.38-10.52 GHz. The core area is $0.49mm^2$ in a $0.13-{\mu}m$ CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.207-212
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• 2013

A new CMOS voltage-bias differential LC voltage-controlled oscillator (LC-VCO) with active source degeneration is proposed. The proposed degeneration technique preserves the quality factor of the LC-tank which leads to improvement in phase noise of VCO oscillators. The proposed VCO shows the high figure of merit (FOM) with large tuning range, low power, and small chip size compared to those of conventional voltage-bias differential LC-VCO. The proposed VCO implemented in 0.18-${\mu}m$ CMOS shows the phase noise of -118 dBc/Hz at 1 MHz offset oscillating at 5.03 GHz, tuning range of 12%, occupies 0.15 $mm^2$ of chip area while dissipating 1.44 mW from 0.8 V supply.

• Korean Journal of Optics and Photonics
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• v.5 no.2
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• pp.217-224
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• 1994

The combination of both phase-shifting convolution and 2-bit quantization smoothing filter was used to reduce speckle noise from saw-tooth speckle fringes phase map, obtained in phase-shifting speckle interferometer. The phase-shifting convolution showed the noise reduction capability of speckle fringe without destroying edge information across 271 jump. Also, it was shown that the 2-bit quantization smoothing filter was superior to average, low-pass filter and median filter in speeding up smoothing process and enhancing SIN ratio. Finally, a path dependent unwrapping algorithm was used to unwrap a noise reduced 271 modulo speckle phasemap. semap.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.903-905
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• 2005

Theoretical expressions are introduced to achieve low phase-noise ring oscillators. Understanding of the relations between the phase-noise and the design parameters leads to the reduction of the phase-noise at the stage of the circuit design. Using expressions from reference, ways of reducing the phase noise are suggested.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.34-40
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• 2004

The PLDRO(Phase-Locked Dielectric Resonator Oscillator) with low phase noise is designed for X-band. The phase of VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is locked to that of a high stable reference oscillator by using a SPD(Sampling Phase Detector) to improve phase noise performance in the loop bandwidth. And, the VCDRO is implemented using a high impedance inverter coupled with dielectric resonator to improve the phase noise performance out of the loop bandwidth. This PLDRO exhibits the harmonic rejection characteristics of 51.67㏈c and requires below 1.95W. The phase noise characteristics are performed as -107.17㏈c/Hz at 10KHz offset frequency and -113.0㏈c/Hz at 100KHz offset frequency, respectively, at ambient. And the output power of 13.0㏈m${\pm}$0.33㏈ is measured over the temperature range of $-20 ∼ +70^{\circ}C$ .

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.695-698
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• 1999

Passive noise reduction is a classical approach to attenuate industrial noise. But Active noise cancellation has several advantages over the passive noise cancellation. Such a system offers a better low frequency performance with a smaller and lighter system. This paper presents an active closed loop control system which consists of an controller for inverting and compensating the phase delay, an microphone for picking up the external noise, and loudspeaker for radiating the acoustic anti-phase signal to reduce external noise. The noise in the phase delay covered from 80$^{\circ}$ to 270$^{\circ}$ tends to be reduced. The degree of noise cancellation obtainable with this system reaches value about 17㏈.