• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.11a
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• pp.143-144
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• 2008

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.3 no.1 s.4
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• pp.13-19
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• 2004

The VCO(Voltage Controlled Oscillator) with low phase noise and high reliability is implemented using nonlinear design, and its phase noise characteristics are compared with that of Lesson's equation. The microstripline coupled with dielectric resonator is realized as a high impedance inverter to improve the phase noise, and the qualify factor of resonator circuit can be transferred to active device with the enhanced the loaded quality factor. The worst case and part stress analyses are achieved to obtain the high reliability of VCO. The developed VCO has the oscillating tuning factor of 0.56MHz/V for the control voltage range of 0$\~$12V This VCO requires the DC power of 160mW. The phase noise characteristics exhibit good performances of -96.51dBc/Hz @ 10KHz and -116.3dBc/Hz @ 100KHz, respectively. And, the output power of 7.33 dBm is measured.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.408-414
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• 2005

The VCDRO(Voltage Controlled Dielectric Resonate. Oscillator) with low phase noise is designed using nonlinear analysis, and its phase noise characteristics are compared with that of Lesson's equation. The microstripline coupled with dielectric resonator is realized as a high impedance inverter to improve the phase noise performance, and the quality factor of resonator circuit can be transferred to active device with the enhanced the loaded quality factor. The worst case and part stress analyses are achieved to obtain the high reliability of VCDRO and the reliability analysis is accomplished to estimate the probability of operation at the end of life. The developed VCDRO has the oscillating tuning factor of 0.56MHZ1V for the control voltage range of 0-l2V. This VCDRO requires the DC power of 136mW. The phase noise characteristics exhibit good performances of -94.18dBc/Hz (a)10KHz and -116.3dBc/Hz (a)100KHz. And, the output power over 7.33dBm is measured.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.8-15
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• 2003

In this paper, the issue of the differential ring oscillator in designing low phase noise is linearity improvement of delay cell's load resistor. A novel differential delay cell that improves on the Maneatis load is proposed. The linearity improvement of load resistor results in lower phase noise in ring oscillator. For comparison of the phase noise characteristics, Ali Hajimiri's phase noise model is used. In order to have a low ISF(impulse sensitivity function), it is important to have a symmetry between rise time and fall time of oscillation waveform. The ISF value of ing oscillator based on the proposed delay cell is lower than that of the existing ring oscillators. Due to this result, the phase noise is improved by 2~3dBc/Hz for the same power dissipation and oscillation frequency.

• Transactions of the Korean Society of Automotive Engineers
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• v.22 no.2
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• pp.107-114
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• 2014

This paper applies a compensated low pass filter (LPF) to current measurements for permanent magnet synchronous motor (PMSM) drives. The noise limits the bandwidth of current controllers and has more adverse influences on control performances under the light load condition because of the low signal-to-noise ratio. In order to eliminate the noise sensitivity, this paper proposes a digital LPF with a compensator of gain attenuation and phase delay which are unacceptable in current information for PMSM drives. Characteristics of the proposed LPF are analyzed in comparison with the general LPFs. The compensated LPF is basically designed by the orthogonal property of the measured currents in the ${\alpha}{\beta}$ stationary reference frame. In addition, an implementation issue of the proposed method is discussed. Experimental results using the proposed method show improvements of the current control performance from two perspectives, rapid step responses and reductions of harmonic distortion.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7A
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• pp.947-954
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• 1999

A new low phase noise Dielectric Resonator Parallel Feedback Oscillator(DRPFO) that is proposed in this paper has a simple structure so that it can be fabricated in low cost and with high performance. The proposed DRPFO is in a feedback loop oscillator configuration, which is composed of a low noise amplifier, a power amplifier, a power attenuator, a power divider and a parallel resonator feedback element that consists of a dielectric resonator coupled with two microstrip lines. The measured phase noise of DRPFO was less than -81 dBc/Hz at offset frequency 1 kHz of 10.75 GHz carrier frequency, and the frequency stability of DRPFO was less than $\pm$200 kHz over the temperature range of -40$^{\circ}$C to +60$^{\circ}$C.

• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.1-9
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• 2012

In this paper, we presents the modeling and implementation of the DDS(Direct Digital synthesizer) driven offset PLL(Pghase Locked Loop) with DAC(Digital Analog Converter) for coarse tune. The PLL synthesizer was designed for minimizing the size and offset frequency and DDS technique was used for ultra low noise and fast lock up time, also DAC was used for coarse tune. The output phase noise was analyzed by superposition theory with the phase noise transfer function and noise source modeling. the phase noise prediction was evaluated by comparing with the measured data. The designed synthesizer has ultra fast lock time within 6 usec and ultra low phase noise performance of -120 dBc/Hz at 10KHz offset frequency.

• 한국초전도학회:학술대회논문집
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• v.12
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• pp.47-47
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• 2002

• Korean Journal of Construction Engineering and Management
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• v.11 no.3
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• pp.55-63
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• 2010

Although the environmental conflicts regarding noise and vibration are continually increasing during construction, noise and vibration occurring in construction are only managed in construction phase. Noise and Vibration occurring in construction are considered to be insufficient, so we find that noise and vibration management in design phase has to be operated for reducing. The objective of this paper is to present noise and vibration management lists to consider in design phase for enhancing efficiency in noise and vibration management and to develop the appraisal sheets for designers to evaluate and the manuals to easily use management lists. To achieve this, we identify the noise and vibration management lists to consider in design phase through analyzing the previous literatures and confirm the 9 lists through conducting a research with experts in environmental area for verifying the propriety of lists. Also, this study applies to AHP technique to identify the priority and the weight evaluation among the lists. Through this study, we identify the most efficient lists, including from the low noise and low vibration methods, the noise and vibration reduction by blasting works, the installment and the arrangement of noise and vibration control equipments, for noise and vibration management in design phase. The achievement of this study will help to prevent the environmental disputes and conflicts in advance and will consider utilizing for the successful construction project.