• Journal of Electrical Engineering and Technology
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• 제12권3호
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• pp.1187-1194
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• 2017

In this paper, a high step-up DC-DC PWM converter with continuous input current and low voltage stress is presented for renewable energy application. The proposed converter is composed of a boost converter integrated with an auxiliary step-up circuit. The auxiliary circuit uses an additional coupled inductor and a balancing capacitor with voltage doubler and switching capacitor technique to achieve high step-up voltage gain with an appropriate switch duty cycle. The switched capacitors are charged in parallel and discharged in series by the coupled inductor, stacking on the output capacitor. In the proposed converter, the voltage stress on the main switch is clamped, so a low voltage switch with low ON resistance can be used to reduce the conduction loss which results in the efficiency improvement. A detailed discussion on the operating principle and steady-state analyses are presented in the paper. To justify the theoretical analysis, experimental results of a 200W 40/400V prototype is presented. In addition, the conducted electromagnetic emissions are measured which shows a good EMC performance.

• 대한전자공학회논문지SD
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• 제43권1호
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• pp.1-6
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• 2006

본 논문에서는 VTCMOS(Variable-Threshold CMOS) 기법을 이용하는 초저전압 구동 논리 회로의 누설 전류 억제를 위한 기판 전압 발생회로를 제안한다. 제안하는 기판 전압 발생회로는 VSS 발생회로와 VBB 발생회로로 구성되어 있다. VSS 발생회로는 네거티브 전압을 발생시켜 VBB 발생회로에 공급하며, nB 발생회로는 공급받은 네거티브 전압을 이용하여 또 다른 네거티브 전압을 발생시킨다. 제안하는 회로의 동작을 검증하기 위해서 0.18um 1Poly-6Metal CMOS 공정을 사용하여 회로를 구현하였으며, 측정 결과 -0.95V의 기판 전압을 얻을 수 있었다. 제안한 기판 전압 발생회로를 이용함으로써, 0.5V의 전원 전압에서 동작하는 논리 회로의 누설 전류 성분을 효과적으로 줄일 수 있다.

• Nuclear Engineering and Technology
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• 제51권4호
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• pp.1081-1090
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• 2019

Detailed pulse shape analysis of a Geiger-$M{\ddot{u}}ller$ counter is performed to understand the pulse shape dependence on operating voltage. New data is presented to demonstrate that not all pulses generated in a GM counter are identical. In fact, there is a strong correlation between the operating voltage and the pulse shape. Similar to detector deadtime, pulse shapes fall in three distinct regions. For low voltage region, where deadtime was reported to reduce with increasing voltage, pulse generated in this region was observed to have a fixed pulse width with a variable tail. The pulse width and fall time of the tail was observed to be a function of applied voltage; exponentially reducing with increasing voltage with an exponent of negative 6E-04 and 2E-03 respectively. The second region showed a pulse without any significant tail. During this time the detector deadtime was earlier reported to be at its minimum. The highest voltage region demonstrated a different deadtime mechanism where the second pulse was reduced in width. During this time the deadtime seemed to be increasing with increasing voltage. This data allows us to gain some unique insight into the phenomenon of GM detector deadtime not reported thus far.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 F
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• pp.1931-1933
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• 1998

In this paper, single-phase PWM AC to AC converter that operates with unit power factor and sinusoidal input line currents is presented. The output voltage of this converter is able to be obtain step up voltage as well as step down voltage. because the converter applies to operating method of buck-boost converter. The control of this converter is performed with PI control method. By using this control method low lipples in the output current and the voltage as well as fast dynamic response are achieved.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1206-1209
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• 2007

Both PM-OLEDs and AM-OLEDs are now in production. However, manufacturers are still concerned about life-time, voltage drift, operating voltage and efficiency in order to develop larger displays. Most material suppliers seem to be focussing on emitters and the benefits of introducing suitable charge transporters have been largely unexplored. OLED-T has developed a novel organic electron injector (Trade Name: EI-101) which evaporates at a very low temperature of $300^{\circ}C$ as opposed to the conventional LiF which requires $580^{\circ}C$. EI-101 has been found to increase the lifetime by up to 12%, reduce the voltage drift by up to 61% and increase the efficiency by up to 15%. The material can be handled in air and in situ Q-mass spectroscopy on extended thermal evaporation has confirmed its high stability for use in mass production.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.40-40
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• 2008

$InGaZnO_4$ based thin film transistors (TFTs) are of interest for large area and low cost electronics. The TFTs have strong potential for application in flat panel displays and portable electronics due to their high field effect mobility, high on/off current ratios, and high optical transparency. The application of such room temperature processed transistors, however, is often limited by the operation voltage and long-tenn stability. Therefore, attaining an optimum thickness is necessary. We investigated the thickness dependence of a room temperature grown $MgO_{0.3}BST_{0.7}$ composite gate dielectric and an $InGaZnO_4$ (IGZO) active semiconductor on the electrical characteristics of thin film transistors fabricated on a polyethylene terephthalate (PET) substrate. The TFT characteristics were changed markedly with variation of the gate dielectric and semiconductor thickness. The optimum gate dielectric and active semiconductor thickness were 300 nm and 30 nm, respectively. The TFT showed low operating voltage of less than 4 V, field effect mobility of 21.34 cm2/$V{\cdot}s$, an on/off ratio of $8.27\times10^6$, threshold voltage of 2.2 V, and a subthreshold swing of 0.42 V/dec.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1038-1041
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• 2006

We report low operating voltage and long lifetime organic light-emitting diodes (OLEDs) with a vanadium oxide $(V_2O_5)-doped$ N,N'-di(1-naphthyl)- N,N'-diphenylbenzidine $({\alpha}-NPD)$ layer between indium tin oxide and ${\alpha}-NPD$. At a luminance of $1000\;cd/m^2$, $V_2O_5$ doped ${\alpha}-NPD$ device shows a operation voltage of 5.1V, while the device without $V_2O_5$ shows 5.8V. The $V_2O_5$ doped $({\alpha}-NPD)$ device also shows a longer lifetime and smaller operation voltage variation over time. It is suggested that the improved device performance can be attributed to the higher hole-injection efficiency and stability of the $V_2O_5$ doped $({\alpha}-NPD)$ layer.

• 한국통신학회논문지
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• 제22권2호
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• pp.361-370
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• 1997

In this paper, we designed POCSAG Signal Decoder to improve operating time in pager. We showed POCSAG Signal Pattern sent by transmitter and operation of this decoder. We also showed that the Pager using this decoder was equipped with Wide Area Signal Detection and designed the hardware which realizes this operation and implemented it with ASIC chip. As we inspected the function of the ASIC chip and tested the performance, we could find that the chip operated in low voltage and that power dissipation was low.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1097-1100
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• 1998

In this paper, the PLL(Phase-Locked Loops) for low voltage and high speed operation is described. In other to obtaining above objects, new CMOS circuit technologies have been used in the each block circuit of PLL. It operates with a lock range from 110 up to 700 MHz and has a peak to peak jitter of 50 ps at operating frequency of 250 MHz. It was fabricated in a $0.6\mu\textrm{m}$ CMOS technology and dissipated 45 mW from a single 3.3V.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.