• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.175-178
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• 2005

In this paper, a carrier frequency offset (CFO) estimator is proposed for the interleaved OFDMA uplink systems. It is based on the estimation of signal parameters via rotational invariance technique (ESPRIT). Compared with the Cao's estimator, the proposed estimator has low computational complexity. Simulation results demonstrate that the proposed estimator performs better than Cao's estimator at the relatively low SNR region. Hence, the proposed estimator is more applicable to the practical environments than the Cao’s estimator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12A
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• pp.1296-1302
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• 2007

In this paper, we propose joint estimation methods of carrier offset and channel estimation for MB-OFDM system with low complexity. The proposed methods estimate the channel by using low-rank LMMSE channel estimation which reduces the system complexity by applying the optimal number of rank to evaluate the frequency offset and additionally using the simple algorithm using the auto-correlation property of the estimated channel. We simulate the proposed algorithms under the IEEE 802.15 TG3a UWB channel model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.60-67
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• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.641-648
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• 2011

Frequency domain equalization is the most promising technology that has relatively low complexity in multipath channel. A frame of single carrier system with frequency domain equalization (SC-FDE) has cyclic prefix to mitigate effect of delay spread. After synchronization and equalization procedure on the SC-FDE system, common phase offset (CPO) that can introduce performance degradation caused by phase mismatch between transmitter and receiver oscillators is remained. In this paper, common phase offset tracking in frequency domain is proposed. To track CPO, constant amplitude zero autocorrelation code sequence as training sequence is adopted. By using numerical results, performance of mean square error is evaluated. The results show that MSE of CPO has similar performance compare to the time-domain estimation and there is no need of domain conversion.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.471-475
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• 2010

This paper presents a frequency synthesizer using low voltage active inductor VCO(Voltage Controlled Oscillator). The low voltage active inductor VCO with feedback resistor increases its equivalent inductance and the quality-factor(Q). Under certain conditions, the low voltage active inductor with feedback resistor generates a negative resistance at the input. In this paper, the conditions for negative resistance are obtained by small signal analysis. The designed low voltage active inductor VCO covers a frequency band between 1059MHz and 1223MHz. The measured phase noise at 1.178GHz is -81.8dBc/Hz at 1MHz offset.

• Journal of information and communication convergence engineering
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• v.16 no.3
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• pp.197-202
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• 2018

This paper reveals the impact of the insertion of electromagnetic band gap (EBG) structures on the performance of circularly polarized (CP) patch-slot antenna with offset slot. Several optimizations are necessary to precise physical parameters in the aim to fix the resonance frequency at 3.2 GHz. The proposed antenna possesses lightweight, simplicity, low cost, and circular polarization ensured by two feeding sources to permit right-hand and left-hand circular polarization process (RHCP and LHCP). The measured results compared with simulation results of the proposed circularly polarized EBG antenna with offset slot show good band operations with –10 dB impedance bandwidths of 9.1% and 36.2% centered at 3.2 GHz, which cover weather radar, surface ship radar, and some communications satellites bands. Our investigation will confirm the simulation and experimental results of the EBG antenna involving new EBG structures.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.155-159
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• 2003

This paper presents fully integrated 5 GHz band low phase noise LC tank VCO. The implemented VCO is tuned by integrated PN diode and tuning rage is $5.01{\sim}5.30$ GHz under $0{\sim}3 V$ control voltage. For good phase noise performance, LC filtering technique, common in Si CMOS process, is used, and to prevent degradation of phase noise performance by collector shot-noise and to reduce power dissipation the HBT is biased at low collector current density bias point. The measured phase noise is -87.8 dBc/Hz at 100 kHz offset frequency and -111.4 dBc/Hz at 1 MHz offset frequency which is good performance. Moreover phase noise is improved by roughly 5 dEc by LC filter. It is the first experimental result in InGaP/GaAs HBT process. The figure of merit of the fabricated VCO with LC filter is -172.1 dBc/Hz. It is the best result among 5 GHz InGaP HBT VCOs. Moreover this work shows lower DC power consumption, higher output power and more fixed output power compared with previous 4, 5 GHz band InGaP HBT VCOs.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.158-162
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• 2015

A low phase noise CMOS voltage controlled oscillator(VCO) for multi-band/multi-standard RF Transceivers is presented. For both wide tunability and low phase noise characteristics, Hybrid inductor which uses both bondwire inductor and planar spiral inductor in the same area, is proposed. This approach reduces inductance variation and presents high quality factor without custom-designed single-turn inductor occupying large area, which improves phase noise and tuning range characteristics without additional area loss. An LC VCO is designed in a 0.13um CMOS technology to demonstrate the hybrid inductor concept. The measured phase noise is -121dBc/Hz at 400KHz offset and -142dBc/Hz at 3MHz offset from a 900MHz carrier frequency after divider. The tuning range of about 28%(3.15 to 4.18GHz) is measured. The VCO consumes 7.5mA from 1.3V supply and meets the requirements for GSM/EDGE and WCDMA standard.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3A
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• pp.265-271
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• 2009

This paper proposes an efficient initial frequency estimator for Digital Video Broadcasting-Second Generation (DVB-S2). The initial frequency offset of the DVB-S2 is around ${\pm}5MHz$, which corresponds to 20% of the symbol rate at 25Msps. To estimate a large initial frequency offset, the algorithm which call provide a large estimation range is required. Through the analysis of the data-aided (DA) algorithms, we find that the Mengali and Moreli (M&M) algorithm can estimate a large initial frequency offset at low SNR. Since the existing frequency estimator based on M&M algorithm has a high hardware complexity, we propose the methods to reduce the hardware complexity of the initial frequency estimator. This can be achieved by reducing the number of autocorrelators and arctangents. The proposed architecture can reduce the hardware complexity about 64.5% compared to the existing frequency estimator and has been thoroughly verified on the Xilinx Virtex II FPGA board.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.754-764
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• 2001

Class A bipolar second-generation current conveyor (CCII) with low current-input impedance and its offset-compensated CCII for high-accuracy current-mode signal processing are proposed. The CCIIs consist of a regulated current-cell for current input, a emitter follower for voltage input, and a cascode current mirror lot current output. In these architecture, the two input stages are coupled by current mirror to reduce the current input impedance. Experiments show that the CCII has impedance of 8.4 Ω and offset voltage of 40 mV at current input terminal. To reduce this offset, the offset-compensated CCII adopts diode-connected npn and pnp transistor in the proposed CCII. Experiments show that the offset-compensated CCII has current input impedance of 2.1 Ω and offset voltage of 0.05 mV. The 3-dB cutoff frequency of the CCIIs when used as a voltage follower extends beyond 30 MHz. The power dissipation is 7.0 mW