• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.122-128
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• 2005

In this paper, a low noise parallel feedback oscillator for harmonic suppression and a frequency doubler are designed and implemented. As the fundamental signal of the oscillator for frequency doubling is extracted between the dielectric resonator (DR) filter and the gate device of the active device, the undesired harmonics at the output of the oscillator is remarkably suppressed. The fundamental signal of the oscillator for frequency doubling directly feeds to the frequency doubler without an additional band pass filter for harmonic suppression. The second harmonic suppression of -47.7 dBc at the oscillator output is achieved, while the fundamental suppression of -37.5 dBc at the doubler output is obtained. The phase noise characteristics are -80.3 dBc/Hz and -93.5 dBc/Hz at the offset frequency of 10 KHz and 100 KHz from the carrier, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.6
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• pp.691-699
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• 2012

In this paper, we present a Vt-DRO with a low phase noise, which is achieved by improving the coupling structure between the dielectric resonator and microstrip line. The Vt-DRO is a closed-loop type and is composed of 3 blocks; dielectric resonator, phase shifter, and amplifier. We propose a mathematical estimation method of phase noise, using the group delay of the resonator. By modifying the coupling structure between the dielectric resonator and microstrip line, we achieved a group delay of 53 nsec. For convenience of measurement, wafer probes were inserted at each stage to measure the S-parameters of each block. The measured S-parameter of the Vt-DRO satisfies the open-loop oscillation condition. The Vt-DRO was implemented by connecting the input and output of the designed open-loop to form a closed-loop. As a result, the phase noise of the Vt-DRO was measured as -132.7 dBc/Hz(@ 100 kHz offset frequency), which approximates the predicted result at the center frequency of 5.3 GHz. The tuning-range of the Vt-DRO is about 5 MHz for tuning voltage of 0~10 V and the power is 4.5 dBm. PFTN-FOM is -31 dBm.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.110-118
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• 2013

This paper describes the development of DSSS wireless communication uplink system for missile remote control. In consideration of low probability of intercept, low probability of exploitation, anti-jam, low latency, and doppler frequency offset, we used DSSS partially DBPSK. Also we used the selective diversity with two receiving antennas to mitigate multipath interference which is the dominant channel impairment and the turbo product code(TPC) for forward error correction(FEC) to improve bit error rate performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.2
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• pp.187-195
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• 1999

A series feedback DRO operating at 3.2 GHz applicable to the spectrum analyzer as the second local oscillator, is designed and fabricated. We can obtain a low noise by utilizing the small signal S-parameter of the transistor and adjusting the reflection coefficient from the coupling coefficient between dielectric resonator and microstrip line. The results show that output power is 10.50 dBm, a stable low phase noise is -116 dBc/Hz at a 10 kHz offset frequency and a harmonic characteristic is 19.33 dBc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.64-72
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• 2010

This paper presents a wide range VCO with fine coarse tuning step using a sigma-delta modulation technique for UWB frequency synthesizer. The proposed coarse tuning scheme provides the low effective frequency resolution without any degradation of phase noise performance. With three steps coarse tuning, the VCO has wide tuning range and fine tuning step simultaneously. The frequency synthesizer with VCO was implemented with 0.13 ${\mu}m$ CMOS technology. The tuning range of the VCO is 5.8 GHz~6.8 GHz with the effective frequency resolution of 3.9 kHz. It achieves the measured phase noise of -108 dBc/Hz at 1 MHz offset and a tuning range 16.8 % with 5.9 mW power. The figure-of-merit with the tuning range is -181.5 dBc/Hz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.613-623
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• 2012

In this paper, we present an ultra miniaturized voltage tuned oscillator, with HMIC-type amplifier and phase shifter, using LTCC artificial dielectric resonator. ADR which consists of periodic conductor patterns and stacked layers has a smaller size than a dielectric resonator. The design specification of ADR is obtained from the design goal of oscillator. The structure of the ADR with a stacked circular disk type is chosen. The resonance characteristic, physical dimension and stack number are analyzed. For miniaturization of ADRO, the ADR is internally implemented at the upper part of the LTCC substrate and the other circuits, which are amplifier and phase shifter are integrated at the bottom side respectively. The fabricated ADRO has ultra small size of $13{\times}13{\times}3mm^3$ and is a SMT type. The designed ADRO satisfies the open-loop oscillation condition at the design frequency. As a results, the oscillation frequency range is 2.025~2.108 GHz at a tuning voltage of 0~5 V. The phase noise is $-109{\pm}4$ dBc/Hz at 100 kHz offset frequency and the power is $6.8{\pm}0.2$ dBm. The power frequency tuning normalized figure of merit is -30.88 dB.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.272-281
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• 2013

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

• Journal of the Korean Society for Railway
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• v.20 no.4
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• pp.448-457
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• 2017

In this paper, for high speed railway propulsion systems, a single phase PWM Converter using discontinuous PWM (DPWM) was investigated. The conventional PWM Converter uses a low frequency modulation index of less than 10 to reduce switching losses due to high power characteristics, which results in low control frequency bandwidth and requires an additional compensation method. To solve these problems, the DPWM method, which is commonly used in three phase PWM Inverters, was adopted to a single phase PWM Converter. The proposed method was easily implemented using offset voltage techniques. Method can improve the control performance by doubling the frequency modulation index for the same switching loss, and can also bring the same dynamic characteristics among switches. Proposed DPWM method was verified by simulation of 100 kW PWM converter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.212-215
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• 2016

In this paper, a 5.08 GHz Ring Voltage Controlled Oscillator(Ring VCO) was implemented using $0.18{\mu}m$ standard CMOS technology. The proposal Ring VCO is 3-stage structure. This research confirmed that the each stage's different transistor size ratio influence the current change and alter power consumption consequentially. This circuit is formed to control the current thereby adding the Current Mirror and to tune the frequency by supplying control voltage. It has an 65.5 %(1.88~5.45 GHz) tuning range. The measured output power is -0.30 dBm. The phase noise is -87.50 dBc/Hz @1 MHz offset with operating frequency of 5.08 GHz fundamental frequency. The total power consumption of Ring VCO is 31.2 mW with 2.4 V supply voltage.