• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.5
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• pp.515-525
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• 2014

In this paper, we present a design and implementation of a Voltage-tuned Planar Composite Resonator Oscillator(Vt-PCRO) with a low phase noise. The designed Vt-PCRO is composed of a resonator, two phase shifters, and an amplifier. The resonator is designed using a dual mode SIW(Substrate Integrated Waveguide) resonator and has a group delay of about 40 nsec. Of the two phase shifters (PS1 and PS2), PS1 with a phase shift of $360^{\circ}$ is used for the open loop gain to satisfy oscillation condition without regard to the electrical lengths of the employed microstrip lines in the loop. PS2 with a phase shift of about $70^{\circ}$ is used to tune oscillation frequency. The amplifier is constructed using two stages to compensate for the loss of the open loop. Through the measurement of the open loop gain, the tune voltage of the PS1 can be set to satisfy the oscillation condition and the loop is then closed to form the oscillator. The oscillator with a oscillation frequency of 5.345 GHz shows a phase noise of -130.5 dBc/Hz at 100 kHz frequency offset. The oscillation power and the electrical frequency tuning range is about 3.5 dBm and about 4.2 MHz for a tuning voltage of 0~10 V, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.8
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• pp.1326-1333
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• 2016

It is important to clear the fault and prevent resulting in damage to power system. Although the frequency of generator internal fault is relatively low, it can lead to incalculable damage to power system as well as generator. Especially, loss of field on generator can cause the generator to lose synchronism for a short time if it is not removed promptly. Therefore, it is needed to conduct research on loss of field relay for detecting or clearing the loss of field. However, the setting of the relay may vary in generator operator or engineer, and the relay is not coordinated well with other elements associated with loss of field. In this paper, we address specifically the coordination of positive offset mho loss of field relay which is one of the protection schemes for loss of field. Computer simulations are performed by using ElectroMagnetic Transients Program-Restructured Version (EMTP-RV) based on actual data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.50-55
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• 2008

In this paper, New LC VCO with $8{\sim}10.9$ GHz Band has been designed using commercial $0.35-{\mu}m$ CMOS technology. This proposed circuit is consisted of the parallel construction of the typical NMOS and PMOS cross-coupled pair which is based on the LC tank, MOS cross-coupled pair which has same tail current of complementary NMOS and PMOS, and output buffer. The designed LC VCO, which is according to proposed structure in this paper, takes a 29% improvement of the wide tuning range as 8 GHz to 10.9 GHz, and a 6.48mW of low power dissipation. Its core size is $270{\mu}m{\times}340{\mu}m$ and its phase noise is as -117dBc Hz and -137dBc Hz at 1-MHz and 10-MHz offset, respectively. FOM of the new proposed LC VCO gets -189dBc/Hz at a 1-MHz offset from a 10GHz center frequency. This design is very useful for the 10Gb/s clock generator and data recovery integrated circuit(IC) and SONET communication applications.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.1
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• pp.85-91
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• 2012

In this paper, we implemented a Ka-band frequency synthesizer for millimeter wave seeker. we designed for high frequency resolution and frequency hopping response time in the digital synthesis method which uses DDS(Direct Digital Synthesizer). but frequency bandwidth was limited low frequency because DDS output frequency was limited 1/2 by system clock. thus, frequency synthesizer was converted to Ka-band using the frequency multiplier ${\times}4$ and local oscillator. proposed frequency synthesizer was bandwidth 500MHz, frequency switching time was $0.7{\mu}s$, spurious level was suppressed below -52dBc. phase noise was -99dBc/Hz at offset 100kHz and flatness was ${\pm}1dB$.

• ETRI Journal
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• v.26 no.3
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.4
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• pp.80-87
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• 2007

In this paper, link-level performance of a OFDMA technique, which has been considered as a standard for 802.16, 802.20, 3G-LTE, WiMax, and WiBro, is evaluated for next-generation wireless communication systems. While many researches have focused on uncoded forward-link performances, this paper provides a coded performance of a reverse-link OFDMA system. Performance degradation due to time offset among reverse-link users and frequency offset during FFT process is investigated. Transmitter and receiver antenna diversity techniques are used to overcome performance degradation. Performance of a OFDMA system is compared with a CDMA system in terms of FER and throughput to emphasize the advantage of OFDMA system for a reverse-link. Finally, under given specification, Eb/No required to achieve the maximum throughput of a reverse-link is proposed considering various coded rates and antenna permutations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6A
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• pp.583-591
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• 2008

OFDM (orthogonal frequency division multiplexing) has serious problem of high PAPR (peak-to-average power ratio). Recently, CI/OFDM (carrier interferometry OFDM) system has been proposed for the low PAPR. However, CI/OFDM system shows another problem of ICI because of phase offset mismatch due to the phase noise. In this paper, to simultaneously reduce the PAPR and ICI effects, we propose an A-CI/OFDM (advanced-CT/OFDM). This method improves the BER performance by use of the margin of phase offset at CI codes. Propose system to reduce the effect the phase noise, even though it shows a little bit higher PAPR than conventional CI/OFDM, so we apply the PTS among the PAPR reduction techniques to proposed system to mitigate this problem. Therefore, it improves the total BER performance because the proposed method can decrease the effect of phase noise and get the gain in PAPR reduction performance. From the simulation results, we can show the performance comparison between the conventional OFDM, CI/OFDM and A-CI/OFDM.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.6
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• pp.552-559
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• 2002

The EM(Engineering Model) LO(Local Oscillator) is designed for Ka-band satellite transponder. The VCO(Voltage Controlled Oscillator) is implemented using a high impedance inverter coupled with dielectric resonator to improve the phase noise performance out of the loop bandwidth. The phase of VCO is locked to that of a stable OCXO(Oven Controlled Crystal Oscillator) by using a SPD(Sampling Phase detector) to improve phase noise performance in the loop bandwidth. This LO exhibits the harmonic rejection characteristics above 43.83 dBc and requires 15 V and 160 mA. The phase noise characteristics are performed as -102.5 dBc/Hz at 10 KHz offset frequency and -104.0 dBc/Hz at 100 KHz offset frequency, respectively, with the output power of 13.50 dBm$\pm$0.33 dB over the temperature range of -20~+7$0^{\circ}C$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1652-1656
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• 2014

In this work, we demonstrated a 77 GHz waveguide VCO with transition from WR-12 to WR-10 for anti-collision radar applications. The fabricated waveguide VCO consists of a GaAs-based Gunn diode, a varactor diode, a waveguide transition, and two bias posts for operating as a LPF and a resonator. The cavity is designed for fundamental mode at 38.5 GHz and operated at second hormonic of 77 GHz. The waveguide transition has a 1.86 dB of insertion loss and -30.22 dB of S11 at the center frequency of 77 GHz. The fabricated VCO achieves an oscillation bandwidth of 870 MHz. Output power is from 12.0 to 13.75 dBm and phase noise is -100.78 dBc/Hz at 1 MHz offset frequency from the carrier.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.1
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• pp.65-73
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• 2007

This paper presents an on-line correction method of current measurement errors for a pure-integration-based flux estimation down to 1-Hz stator frequency. An observer-based approach is taken as one possible solution of eliminating the dc offset and the negative sequence component of unbalanced gains in the synchronous coordinate. At the same time, the positive sequence component estimation is performed by creating an error signal between a motor model reference and an estimated q-axis rotor flux established by a permanent magnet (PM) in the synchronous coordinate. The compensator utilizes a PI controller that controls the error signal to zero. The proposed technique further contains a residual error compensator to completely eliminate miscellaneous disturbances in the estimated flux. The developed algorithm has been implemented on a 1.1-kW permanent magnet synchronous motor (PMSM) drive to confirm the effectiveness of the proposed scheme.