• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.1
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• pp.1-6
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• 2007

In this paper, a simplified new modulation classification method that utilizes likelihood function for received signal in an impaired AWGN channel environment. The proposed method provides the superior to ML method, although the likelihood under the assumption that each modulated signal is sent utilized. On the other hand, the ML method gets the performance characteristics of high computational complexity and weakness to channel impairment such as phase offsets and frequency offsets. The proposed method has lower computational complexity than that of the ML method. Moreover, the proposed method is robust to the channel impairment such as phase offsets and frequency offsets. The correct classification probabilities of the proposed method and the ML method are given for an AWGN channel with phase offsets and frequency offsets, which were simulated with extensive Monte-Carlo simulation. As shown in simulation resole, a more accurate classification performance both in phase offset environment and in frequency offset can be achieved with the low computational complexity of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.5
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• pp.69-76
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• 2004

In this paper, a VCDRO (Voltage Control Dielectric Resonator Oscillator) with low phase noise for X-band application has been designed and fabricated. A low noise and low flicker noise MESFET and a high Q dielectric resonator were selected to obtain good phase noise Performance. Also, a varactor diode having high Q, qualify factor was used to reduce the loading effects and a big Gamma of diode was chosen for linearity of frequency over voltage tuning range. The fabricated circuits was simulated with circuit design tools, ADS to provide the optimum performances. As the measured results of fabricated oscillator, the output power was 5.8 ㏈m at center frequency 12.05㎓ and harmonic suppression -30㏈c, phase noise -114 ㏈c at 100 KHz offset frequency, respectively, and the frequency tuning range as the function of valtage applied to varactor diode was 15.2 MHz and its power variation with frequency was 0.2 ㏈. This oscillator could be available to a local oscillator in X-band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.627-634
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• 2010

In this paper, a novel voltage-controlled oscillator(VCO) using the complimentary bifilar archimedean spiral resonator(CBASR) is presented for reducing the phase noise characteristic. A CBASR has compact dimension, a sharp skirt characteristic in stopband, a low insertion loss in passband, and a large coupling coefficient value, which makes a high Q value and improve the phase noise of VCO. The proposed VCO has the oscillation frequency of 2.396~2.502 GHz in the tuning voltage of 0~5 V, the output power of 7.5 dBm and phase noise of -119.16~-120.2 dBc/㎐ at the offset frequency of 100 kHz in tuning range.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.9
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• pp.967-973
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• 2003

This paper presents a new predistortion method which injects the 2nd low-frequency intermodulation signal of RF signals into the input bias line of the amplifier. New 2nd intermodulation signal extraction circuit is also proposed. We have shown that this method can suppress the 3rd IM apparently and sometimes do the 5th IM, through mathematical analysis, then confirmed it with simulation and verified it on the desk test. When the input signal CDMA IS-95 lFA is applied, measured ACPR improvements are 25 dBc, 22.5 dBc, and 6 dBc at 0.885 MHz, l.25 MHz and 2.25 MHz offset respectively. Also, when applying the CDMA IS-95 3FA, the measured ACPR improvement is 20 dBc at 0.885 MHz offset.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.34-40
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• 2004

The PLDRO(Phase-Locked Dielectric Resonator Oscillator) with low phase noise is designed for X-band. The phase of VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is locked to that of a high stable reference oscillator by using a SPD(Sampling Phase Detector) to improve phase noise performance in the loop bandwidth. And, the VCDRO is implemented using a high impedance inverter coupled with dielectric resonator to improve the phase noise performance out of the loop bandwidth. This PLDRO exhibits the harmonic rejection characteristics of 51.67㏈c and requires below 1.95W. The phase noise characteristics are performed as -107.17㏈c/Hz at 10KHz offset frequency and -113.0㏈c/Hz at 100KHz offset frequency, respectively, at ambient. And the output power of 13.0㏈m${\pm}$0.33㏈ is measured over the temperature range of $-20 ∼ +70^{\circ}C$ .

• ETRI Journal
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• v.41 no.6
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• pp.829-837
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• 2019

The p-type nanowire field-effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in-depth technology computer-aided design (TCAD) with quantum models for sub-10-nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence-band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L_g) by examining a set of primary DC and AC parameters. The cutoff frequency (f_T) and maximum oscillation frequency (f_max) of the proposed device were determined to be 440.0 and 753.9 GHz when L_g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe-shell channel p-type nanowire FET has demonstrated a strong potential for low-power and high-speed applications in 10-nm-and-beyond complementary metal-oxide-semiconductor (CMOS) technology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.4
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• pp.335-344
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• 2004

A low phase noise EQM(Engineering Qualified Model) LO(Local Oscillator) has been developed for Ka-band satellite transponder. A VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is also designed using a high impedance inverter coupled with dielectric resonator to improve the phase noise performances out of the loop bandwidth. The mechanical analysis fur housing and the thermal analysis fur circuit board are achieved. This EQM LO is applied to Ka-band satellite transponder of EQM level after environmental experiments for space application. The LO has the harmonic suppression characteristics above 52 ㏈c and requires low power consumption under 1.3 watts. The phase noise characteristics are exhibited as -101.33 ㏈c/㎐ at 10 ㎑ offset frequency and -114.33 ㏈c/㎐ at 100 ㎑ offset frequency, with the output power of 14.0 ㏈m${\pm}$0.17 ㏈ over the temperature range of -15∼＋65$^{\circ}C$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.675-681
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• 2016

A 41dB gain control range $6^{th}$-order band-pass receiver front-end (RFE) using CMOS switched frequency translated impedance (FTI) is presented in a 40 nm CMOS technology. The RFE consists of a frequency tunable RF band-pass filter (BPF), IQ gm cells, and IQ TIAs. The RF BPF has wide gain control range preserving constant filter Q and pass band flatness due to proposed pre-distortion scheme. Also, the RF filter using CMOS switches in FTI blocks shows low clock leakage to signal nodes, and results in low common mode noise and stable operation. The baseband IQ signals are generated by combining baseband Gm cells which receives 8-phase signal outputs down-converted at last stage of FTIs in the RF BPF. The measured results of the RFE show 36.4 dB gain and 6.3 dB NF at maximum gain mode. The pass-band IIP3 and out-band IIP3@20 MHz offset are -10 dBm and +12.6 dBm at maximum gain mode, and +14 dBm and +20.5 dBm at minimum gain mode, respectively. With a 1.2 V power supply, the current consumption of the overall RFE is 40 mA at 500 MHz carrier frequency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.291-294
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• 2003

The circuit substrate was made from the Low Temperature Cofired Ceramics(LTCC) that a $\varepsilon_\gamma$ was 7.8. Accumulated Varactor and the low noise transistor which were a Surface Mount Device-type element on LTCC substrate. Let passive element composed R, L, C with strip-line of three dimension in the multilayer substrate circuit inside, and one structure accumulate band-pass filter, resonator, a bias line, a matching circuit, and made it. Used Screen-Print process, and made Strip-line resonator. A design produced and multilayer-type VCO(Voltage Controlled Oscillator), and recognized a characteristic with the Spectrum Analyzer which was measurement equipment. Measured multilayer structure VCO is oscillation frequency 1292[MHz], oscillation output -28.38[dBm], hamonics characteristic -45[dBc] in control voltage 1.5[V], A phase noise is -68.22[dBc/Hz] in 100 KHz offset frequency. The oscillation frequency variable characteristic showed 30[MHz/V] characteristic, and consumption electric current is approximately 10[mA].

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.501-503
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• 2008

This paper presents the design of a 2.4 GHz low phase noise fully integrated LC Voltage-Controlled-Oscillator (VCO) in $0.18{\mu}m$ CMOS technology. The VCO is without any tail bias current sources for a low phase noise and, in which differential varactors are adopted for the symmetry of the circuit. At the same time, the use of differential varactors pairs reduces the tuning range, i.e., the frequency range versus VTUNE, so that the phase noise becomes lower. The simulation results show the achieved phase noise of -138.5 dBc/Hz at 3 MHz offset, while the VCO core draws 3.9mA of current from a 1.8V supply. The tuning range is from 2.28GHz to 2.55 GHz.