• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.304-308
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• 2003

A low cost solution employing harmonic oscillation to the frequency synthesizer at 5.8 GHz is proposed. The proposed frequency synthesizer is composed of 2.9GHz PLL chip, 2.9GHz oscillator, and 5.8GHz buffer amplifier. The measured data shows a frequency tuning range of 290MHz, ranging from 5.65 to 5.94GHz, about 0.5dBm of output power, and a phase noise of -107.67 dBc/Hz at the 100kHz offset frequency. All spurious signals including fundamental oscillation power (2.9GHz) are suppressed at least 15dBc than the desired second harmonic signal.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.191-192
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• 2007

This paper presents a 900MHz fractional-N frequency synthesizer for radio frequency identification (RFID) reader using $0.18{\mu}m$ standard CMOS process. The IC meets the EPC Class-1 Generation-2 and ISO-18000 Type-C standards. To minimize VCO pulling, the 900MHz VCO is generated by a 1.8GHz VCO followed by a frequency divider. The settling time of the synthesizer is less than $20{\mu}m$. The frequency synthesizer achieves the phase noise of -105.6dBc/Hz at 200kHz offset. The frequency synthesizer occupies an area of $1.8{\times}0.99mm^2$, and dissipates 8mA from a low supply voltage of 1.8V.

• Journal of Communications and Networks
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• v.6 no.2
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• pp.112-122
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• 2004

A nonlinear spectral-line method utilizing the fourth absolute moment of the receiver discrete Fourier transform output is proposed as a non-data-aided fine carrier frequency synchronization algorithm for OFDM receivers. A simple modification of the algorithm resulting in low implementation complexity is also developed. Analytic expressions are derived for the steady-state frequency error variances of the algorithms and verified to be very accurate via computer simulations over AWGN and frequency selective multipath channels. Numerical results show that the proposed algorithms provide reliable and excellent steady-state performance, especially with PSK modulation. Also, the proposed algorithms are insensitive to symbol timing offsets, only requiring a coarse symbol timing recovery.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.2
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• pp.62-66
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• 2010

In this article, a oscillator at X-band with a double H-shape metamaterial resonator (DHMR) based on high-Q is proposed with metamaterial structure to improve Ihe phase noise and output power. The proposed oscillator is required low phase noise and high output power for the high performance frequency synthesizer. DHMR is designed to be high-Q at resonance frequency through strong coupling of E-field. This character makes phase noise excellent. The oscillator using DHMR is oscillated in X-band so as to apply frequency synthesizer of radar systems. The output power is 4.33 dBm and the phase noise is -108 dBc/Hz at 100 kHz offset of carrier frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.1
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• pp.94-99
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• 1997

There are several factors that have influence on the phase noise of an oscillator. But one of the major factors is the flicker noise of a transistor, since the phase noise of an oscillator is generated by mixing the carrier with the low frequency noise near the DC having the characteristic of 1/f. In this paper, we have presented a method on reducing the phase noise of an oscillator by using a low-frequency feedback circuit based on an active bias circuit, and have fabricated a DRO for a DBS receiver. Measurement results show that the phase noise is -92 dBc/Hz at the 10 KHz offset frequency, and from these results we have found out that the reduction method is very effective.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.7
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• pp.3-9
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• 2015

In this paper, we propose an initial timing and frequency synchronization scheme for low probability detection (LPD) systems with cyclic code shift keying (CCSK). The performance of the LPD system with CCSK highly depend on initial timing and frequency offset. On the other hand, the operating SNR (Signal-to-Noise Ratio) of LPD systems is usually very low. Hence, to guarantee a reliable performance of the LPD system, it is crucial to develop suitable initial synchronization algorithms. In this paper, we propose an initial timing and frequency synchronization scheme suitable for CCSK based LPD system using a repeated preamble pattern.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.61-67
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• 2009

This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.926-934
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• 2016

In this paper, we designed a compact frequency synthesizer with multi-function for Ka-band seeker. DDS(Direct Digital Synthesizer) is applied to generate various waveform and to cover high-speed frequency sweep. In order to reduce size, waveform generator and frequency up-converter are integrated in one module. Proposed frequency synthesizer provides precise detection and tracking waveform for low and high speed targets. It is observed that fabricated synthesizer performs $0.45{\mu}sec$ frequency switching time and -93.69 dBc/Hz phase noise at offset 1 kHz. The size of the synthesizer is kept within 120 mm width, 120 mm length and 22 mm height.

• Journal of IKEEE
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• v.16 no.2
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• pp.121-126
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• 2012

In this paper, a push-push VCDRO (Voltage Controlled Dielectric Resonator Oscillator) with a modified frequency tuning structure is investigated. The push-push VCDRO designed at 16GHz is manufactured using a LTCC (Low Temperature Co-fired Ceramic) technology to reduce the circuit size. The frequency tuning structure is embedded in intermediate layer of A6 substrate by an advantage of LTCC process. Experimental results show that the fundamental frequency suppression is above 30dBc, the frequency tuning range is 0.43MHz over control voltage of 0 to 12V, and phase noise of push-push VCDRO presents a good performance of -103dBc/Hz at 100KHz offset frequency from carrier.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.269-272
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• 2003

A low phase noise frequency synthesizer at X-Band which employs the subharmonic injection locking was designed and tested. The frequency synthesizer consists of two oscillators - master and slave : A 1.75GHz master oscillator made of PLL synthesizer produces 6th harmonic at 10.5GHz, which excites the following 10.5GHz slave oscillator. The realized frequency synthesizer has a 4.5dBm of output power, and a phase noise of -108dBc/Hz at the 100kHz offset frequency.